insertb.vhd

来自「实现HDB3编码,使用VHDL语言」· VHDL 代码 · 共 55 行

--输出端用“11”表示符号“V”，“01”表示“1”码， “00”表示“0”码，“10”表示符号“B”。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity insertb is
 port( clk       :   in   std_logic;
       codeoutv  :   in   std_logic_vector(1 downto 0);
       codeoutb  :   out  std_logic_vector(1 downto 0));
end ;

architecture one of insertb is
  signal reg0   :    std_logic_vector(2 downto 0):="000";
  signal reg1   :    std_logic_vector(2 downto 0):="000";
  signal count1 :    integer range 0 to 1;
  signal firstv :    std_logic:='0';
  signal flag1  :    std_logic:='0';
  begin
 process(clk)
  begin
  if clk'event and clk='1' then                     --行换移位2个3位寄存器  。   
      reg0(0)<=codeoutv(0);
      reg1(0)<=codeoutv(1);
      reg0(1)<=reg0(0);
      reg1(1)<=reg1(0);
      reg0(2)<=reg0(1);
      reg1(2)<=reg1(1); 
  end if;
end process;  
 process(clk)
  begin 
  if clk'event and clk='1' then
     case codeoutv is
        when "11"=>  if firstv='0'  then
                        firstv<='1';count1<=0;
                        codeoutb<=reg1(2)&reg0(2);
                     elsif flag1='0' then
                        codeoutb<="10";
                     elsif count1=1 then              --判断是否插于B码即“10”   
                        count1<=0;
                        flag1<='0';
                        codeoutb<="10";
                     else
                        flag1<='0'; 
                        codeoutb<=reg1(2)&reg0(2);
                     end if;
       when "01"=>   count1<=count1+1;
                     flag1<='1';
                     codeoutb<=reg1(2)&reg0(2);
       when "00"=>   count1<=count1;
                     codeoutb<=reg1(2)&reg0(2);
       when others=>null;
     end case;
  end if;
 end process;
end;