dds.vhd

低频数字相位测量仪仿真的软件部分

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dds is
	port(	
		 frep:   in std_logic_vector(14 downto 0);
		 phase:  in std_logic_vector(8 downto 0); 
		 clk:	 in std_logic;
		 address1:  out std_logic_vector(8 downto 0);
		 address2:	 out std_logic_vector(8 downto 0)
		 );
end;

architecture one of dds is	
signal address: std_logic_vector(8 downto 0);
signal acc:std_logic_vector(23 downto 0); 
begin 		   
	process(clk,phase)
	begin
		if clk'event and clk='1' then
			acc<=acc+frep;
		end if;

	address<=acc(23 downto 15); 
	address1<=address;
    address2<=address+phase;
		end process;  
end one;