counter.vhd

来自「低频数字相位测量仪仿真的软件部分」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is	  
	port(
		CLR32: in std_logic;			
		FIN32: IN std_logic;				
		START32: in std_logic;				
		Q32: OUT std_logic_vector(31 downto 0)
		);
end;		

architecture behav of counter is   
signal Qtemp:std_logic_vector(31 downto 0);
begin
	process(clr32,fin32,start32)
	begin
		if clr32='1' then Qtemp<=(others=>'0'); 
		elsif (fin32'event) and (fin32='1') then
			if start32='1'then
				Qtemp<=Qtemp+1;
			end if;
		end if;
	end process;
	Q32<=Qtemp;
end ;