代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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txt vhdl.txt

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY ad9851 is port(reset:buffer std_logic; clk:in std_logic; data:out std_logic_vector(7 downto 0);
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vhd count.vhd

LIBRARY IEEE; --4位十进制计数器（0~9999） USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count IS PORT(CLKN,ENN,RSTN:IN STD_LOGIC; COUTN:OUT STD_LOGIC; QA,QB,QC,Q
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vhd reg16.vhd

LIBRARY IEEE; --16位锁存器 USE IEEE.STD_LOGIC_1164.ALL; ENTITY reg16 IS PORT(LK:IN STD_LOGIC; DIN1,DIN2,DIN3,DIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT1,DOUT2,DOUT3,DOUT4:OUT STD_LO
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www.eeworm.com/read/467709/7000213

vhd freq.vhd

LIBRARY IEEE; --4位十进制频率计的顶层文件 USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY freq IS PORT(F_IN,CLKKK:IN STD_LOGIC; F_COUT:OUT STD_LOGIC; ZA,ZB,ZC,ZD:OUT S
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www.eeworm.com/read/467840/7002016

vhd cnt_up_down.vhd

--------------------------------------------- Licznik binarny, dwukierunkowy -- -- Licznik binarny, dwukierunkowy, bez zerowania RESET. Warto滄 pocz箃kowa po -- w彻czeniu napi阠ia zasilania to stan
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www.eeworm.com/read/467448/7012807

vhd adder.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(load: in std_logic; a:in std_logic_vector(15 downto 0); b:in std_logic_vector(15
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www.eeworm.com/read/467114/7017807

vhd hour.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity HOUR is port(clk,en:in std_logic; h1,h0:out std_logic_vector(3 downto 0)); end HOUR; architecture hour_
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www.eeworm.com/read/467114/7017849

vhd mian.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mian is port(clk,clr:in std_logic; sec1,sec0:out std_logic_vector(3 downto 0); co:out std_logic); en
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www.eeworm.com/read/467114/7017853

vhd minute.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity MINUTE is port(clk,en:in std_logic; min1,min0:out std_logic_vector(3 downto 0); co:out std_logic);
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www.eeworm.com/read/255028/7019401

vhd andarith.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ANDARITH IS -- 选通与门模块 PORT ( ABIN : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOU
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