andarith.vhd

来自「基于fpga和sopc的用VHDL语言编写的EDA移位相加硬件乘法器」· VHDL 代码 · 共 18 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS                                 -- 选通与门模块
    PORT ( ABIN : IN STD_LOGIC;
         DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END ANDARITH;
ARCHITECTURE behav OF ANDARITH IS
BEGIN
    PROCESS(ABIN, DIN)
    BEGIN
        FOR I IN 0 TO 7 LOOP               -- 循环，完成8位与1位运算
            DOUT(I) <= DIN(I) AND ABIN;
        END LOOP;
    END PROCESS;
END behav;