adder.vhd

来自「多功能函数发生器」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
  port(load: in std_logic;
       a:in std_logic_vector(15 downto 0);
       b:in std_logic_vector(15 downto 0);
       s: out std_logic_vector(15 downto 0));
  end adder;
architecture behav of adder is
begin
process(load)
begin
if load'event and load='1'
   then s<=a+b;
end if;
end process;
end behav;