freq.vhd

来自「四位十进制数字频率计： 测量范围：1Hz～10kHz； 显示时间」· VHDL 代码 · 共 44 行

LIBRARY IEEE; --4位十进制频率计的顶层文件
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY freq IS
   PORT(F_IN,CLKKK:IN STD_LOGIC;
        F_COUT:OUT STD_LOGIC;
       ZA,ZB,ZC,ZD:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END freq;

ARCHITECTURE behav OF freq IS
   COMPONENT ctrl
      PORT(CLKK:IN STD_LOGIC; 
         CNT_EN:OUT STD_LOGIC; 
        RST_CNT:OUT STD_LOGIC; 
        LOAD:OUT STD_LOGIC);
   END COMPONENT;

   COMPONENT count
      PORT(CLKN,ENN,RSTN:IN STD_LOGIC;
           COUTN:OUT STD_LOGIC;
          QA,QB,QC,QD:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
     
   END COMPONENT;

   COMPONENT reg16
     PORT(LK:IN STD_LOGIC;
        DIN1,DIN2,DIN3,DIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       DOUT1,DOUT2,DOUT3,DOUT4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
   END COMPONENT;

   SIGNAL EN1,CLR1,LOAD1:STD_LOGIC;
   SIGNAL Q1,Q2,Q3,Q4:STD_LOGIC_VECTOR(3 DOWNTO 0);

   BEGIN
   U1:ctrl PORT MAP(CLKK=>CLKKK,CNT_EN=>EN1,RST_CNT=>CLR1,LOAD=>LOAD1);
   U2:count PORT MAP(CLKN=>F_IN,ENN=>EN1,RSTN=>CLR1,QA=>Q1,QB=>Q2,QC=>Q3,QD=>Q4,COUTN=>F_COUT);
   U3:reg16 PORT MAP(LK=>LOAD1,DIN1=>Q1,DIN2=>Q2,DIN3=>Q3,DIN4=>Q4,
                    DOUT1=>ZA,DOUT2=>ZB,DOUT3=>ZC,DOUT4=>ZD);

END behav;