count.vhd

来自「四位十进制数字频率计： 测量范围：1Hz～10kHz； 显示时间」· VHDL 代码 · 共 25 行

LIBRARY IEEE; --4位十进制计数器（0~9999）
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count IS
   PORT(CLKN,ENN,RSTN:IN STD_LOGIC;
        COUTN:OUT STD_LOGIC;
        QA,QB,QC,QD:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END count;

ARCHITECTURE behav OF count IS
   COMPONENT cnt10
      PORT(CLK,RST,EN : IN STD_LOGIC;
			     COUT : OUT STD_LOGIC;
           CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
   END COMPONENT;

   SIGNAL COUT1,COUT2,COUT3:STD_LOGIC;

   BEGIN
     U1:cnt10 PORT MAP(CLK=>CLKN,EN=>ENN,RST=>RSTN,CQ=>QA,COUT=>COUT1);
     U2:cnt10 PORT MAP(CLK=>CLKN,EN=>COUT1,RST=>RSTN,CQ=>QB,COUT=>COUT2);
	 U3:cnt10 PORT MAP(CLK=>CLKN,EN=>(COUT1 AND COUT2),RST=>RSTN,CQ=>QC,COUT=>COUT3);
     U4:cnt10 PORT MAP(CLK=>CLKN,EN=>(COUT1 AND COUT2 AND COUT3),RST=>RSTN,CQ=>QD,COUT=>COUTN);
END behav;