代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/421594/10727935
vhd reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0
www.eeworm.com/read/350575/10731439
vhd img.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity img is
port(clk50mhz:in std_logic;
hs,vs,r,g,b:out std_logic);
end img;
architecture behave of img is
componen
www.eeworm.com/read/350575/10731445
vhd imgrom.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity vgarom is
port ( CLK1 : in STD_LOGIC;
A18 : out STD_LOGIC;
OE1 : out STD_LOGIC;
clk: in STD_LOGIC
www.eeworm.com/read/276361/10744082
vhd rs232.vhd
--
--A simple RS232 and PS/2 protocol application.
--The data received from the keyboard will be sent to
--the computer through the RS232 interface.
--And the data received from the computer will be d
www.eeworm.com/read/350245/10754256
vhd tf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tf is
port(ena:in std_logic;
tclk:in std_logic;
clr:in std_logic;
tsq:buffer std_logic_v
www.eeworm.com/read/350245/10754569
vhd tf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity tf is
port(ena:in std_logic;
tclk:in std_logic;
clr:in std_logic;
tsq:buffer std_logic_v
www.eeworm.com/read/350245/10754742
vhd bzq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bzq is
port(bena:in std_logic;
bclk:in std_logic;
clr:in std_logic;
bzq:buffer std_logic_
www.eeworm.com/read/350245/10755127
vhd bzq.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bzq is
port(bena:in std_logic;
bclk:in std_logic;
clr:in std_logic;
bzq:buffer std_logic_
www.eeworm.com/read/350243/10756028
vhd dvf.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dvf is
port (clk:in std_logic;
d:in std_logic_vector(7 downto 0);
fout:buffer std_logic);
end dv
www.eeworm.com/read/420624/10785930
vhd jtd.vhd
library ieee;
use ieee.std_logic_1164.all;
entity jtd is
port(ini ,clk,spe:in std_logic;
ar,ay,ag,al:out std_logic;
br,by,bg,bl:out std_logic;
atime :out std_logic_vector(6 downto 0);
btime :ou