dvf.vhd

数控分频的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dvf is
port (clk:in std_logic;
      d:in std_logic_vector(7 downto 0);
      fout:buffer std_logic);
end dvf;
 
architecture behav of dvf is
signal cnt8:std_logic_vector(7 downto 0):="11111111";
 begin
  process(clk)
    begin
     if clk'event and clk='1' then
       if  cnt8="11111111" then
           cnt8<=d;
           fout<=not fout;
       else cnt8<=cnt8+1;
       end if;
     end if;
  end process;
 end behav;