📄 jtd.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity jtd is
port(ini ,clk,spe:in std_logic;
ar,ay,ag,al:out std_logic;
br,by,bg,bl:out std_logic;
atime :out std_logic_vector(6 downto 0);
btime :out std_logic_vector(6 downto 0));
end jtd;
architecture rtl of jtd is
component ctrl
port(clk,spe:in std_logic;
en:out std_logic);
end component;
component cb
port(clk:in std_logic;
q:buffer std_logic);
end component;
component count
port(ini,en,clk:in std_logic;
ar0,ag0,ay0,al0,br0,bg0,by0,bl0:out std_logic;
tah:buffer std_logic_vector(6 downto 4);
tal:buffer std_logic_vector(3 downto 0);
tbh:buffer std_logic_vector(6 downto 4);
tbl:buffer std_logic_vector(3 downto 0));
end component;
component ltout
port(en,clk:in std_logic;
ar0,ag0,ay0,al0:in std_logic;
br0,bg0,by0,bl0:in std_logic;
ta:in std_logic_vector(6 downto 0);
tb:in std_logic_vector(6 downto 0);
ar,ag,ay,al:out std_logic;
br,bg,by,bl:out std_logic;
atime :out std_logic_vector(6 downto 0);
btime :out std_logic_vector(6 downto 0));
end component;
signal en_s,q_s:std_logic;
signal ar0_s,ag0_s,ay0_s,al0_s,br0_s,bg0_s,by0_s,bl0_s:std_logic;
signal agyl0_s,bgyl0_s:std_logic_vector(2 downto 0);
signal tah_s,tbh_s:std_logic_vector(6 downto 4);
signal tal_s,tbl_s:std_logic_vector(3 downto 0);
signal ta_s,tb_s:std_logic_vector(6 downto 0);
signal agyl,bgyl:std_logic_vector(2 downto 0);
begin
ta_s<=tah_s & tal_s;
tb_s<=tbh_s & tbl_s;
u0:ctrl port map(clk,spe,en_s);
u1:cb port map(clk,q_s);
u2:count port map(ini,en_s,q_s,ar0_s,ag0_s,ay0_s,
al0_s,br0_s,bg0_s,by0_s,bl0_s,tah_s,tal_s,tbh_s,tbl_s);
u3:ltout port map(en_s,q_s,ar0_s,ag0_s,ay0_s,
al0_s,br0_s,bg0_s,by0_s,bl0_s,ta_s,tb_s,ar,ag,ay,al,br,
bg,by,bl,atime,btime);
end rtl;
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