rs232.vhd

串行通信实验

--
--A simple RS232 and PS/2 protocol application.
--The data received from the keyboard will be sent to
--the computer through the RS232 interface.
--And the data received from the computer will be displayed
--on the LCD.
--The data frame is 1 start bit,8 data bits,no parity,and 1 stop bit.
--Baud rate: 19200
--Using the interface on Spartan-3E Starter Kit.
--
--Designed by YK@USTC Nov.,2007.
--
---------------------------------------------------------------------------
--
--Library declarations.
--
--Standard IEEE libraries.
--
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
--
----------------------------------------------------------------------------
--
--Port description.
--
entity rs232 is
    port( CLK_IN  : in std_logic;--System clock(50MHz).
        RST       : in std_logic;--Globle reset.
        PS2_CLK   : in std_logic;--Keyboard clock line.
        PS2_DATA  : in std_logic;-- Keyboard data line.
        RXD       : in std_logic;--RS232_DCE_RXD.
        TXD       : out std_logic;--RS232_DCE_RXD.
        --
        ERR_IND   : out std_logic;--Parity or overflow error.
        DATA_ARV  : out std_logic;--A scan code has arrived.
        --
        --Output pins related to LCD controller.
        --     
        SF_D      : out std_logic_vector(11 downto 8);
        lCD_EN    : out std_logic;
        LCD_RS    : out std_logic;
        LCD_RW    : out std_logic;
        SF_CE0    : out std_logic);
end rs232;
--
-----------------------------------------------------------------------------
--
--Start of architecture.
--
architecture Behavior of rs232 is
--
-----------------------------------------------------------------------------
--
--ps2_st defination.
--
type ps2_data_st is (ps2_idle, ps2_shifting);
type tx_data_st is (tx_idle, tx_start, tx_shifting, tx_stop);
type rx_data_st is (rx_idle, rx_start, rx_null, rx_shifting, rx_stop, rx_err);
--
--Signals.
--
--
--Signals for keyboard.
--
signal clk            : std_logic;
signal PS2_datr       : std_logic;
signal shift_reg      : std_logic_vector(8 downto 0);
signal data_pstn      : std_logic_vector(3 downto 0);
signal key_code       : std_logic_vector(7 downto 0);
signal kbd_data       : std_logic_vector(7 downto 0);
signal filter         : std_logic_vector(7 downto 0);
signal PS2_clk_f      : std_logic;
signal fall_clk       : std_logic;
signal parity         : std_logic;
signal scan_data_arv  : std_logic;
--
signal ps2_st         : ps2_data_st;
--
--Signals for LCD.
-- 
signal s_sf_ce0       : std_logic := '0';--The initial value is useful only
signal lcd_enable     : std_logic := '0';--when simulating.
signal init_over      : std_logic := '0';
signal lcd_data       : std_logic_vector(5 downto 0);
signal clk_cnt1       : std_logic_vector(5 downto 0) := "000000";
signal cnt1           : std_logic_vector(18 downto 0) := "0000000000000000000";
--
--Signals for RS232 port.
--
--///********************************************************************////
signal clk_uart       : std_logic;
signal div_4          : std_logic_vector(1 downto 0);
signal baud_rate      : std_logic;
signal BDRx16         : std_logic;
signal cnt_BDRx16     : std_logic_vector(7 downto 0);
signal cnt_BDR        : std_logic_vector(3 downto 0);
signal temp_data      : std_logic_vector(7 downto 0);
signal tx_data        : std_logic_vector(7 downto 0);
signal tx_reg         : std_logic_vector(9 downto 0);
signal tx_bit_cnt     : std_logic_vector(3 downto 0);
signal tx_busy        : std_logic;
signal rx_sync        : std_logic;
signal rx_smpl_rate   : std_logic;
signal rx_err_ind     : std_logic;
signal rx_data_rdy    : std_logic;
signal rx_bit_cnt     : std_logic_vector(3 downto 0);
signal rx_div         : std_logic_vector(2 downto 0);
signal rx_reg         : std_logic_vector(8 downto 0);
signal rx_data        : std_logic_vector(7 downto 0);
signal rx_code        : std_logic_vector(7 downto 0);
signal PS2_data_vir   : std_logic;
--
signal tx_st          : tx_data_st;
signal rx_st          : rx_data_st;
--///*********************************************************************////
--
---------------------------------------------------------------------------------------
--
function decoding(data : in std_logic_vector(7 downto 0)) return std_logic_vector is 
begin
    case data is 
        when x"1C" => return x"41";--A
        when x"32" => return x"42";--B
        when x"21" => return x"43";--C
        when x"23" => return x"44";--D
        when x"24" => return x"45";--E
        when x"2B" => return x"46";--F
        when x"34" => return x"47";--G
        when x"33" => return x"48";--H
        when x"43" => return x"49";--I
        when x"3B" => return x"4A";--J
        when x"42" => return x"4B";--K
        when x"4B" => return x"4C";--L
        when x"3A" => return x"4D";--M
        when x"31" => return x"4E";--N
        when x"44" => return x"4F";--O
        when x"4D" => return x"50";--P
        when x"15" => return x"51";--Q
        when x"2D" => return x"52";--R
        when x"1B" => return x"53";--S
        when x"2C" => return x"54";--T
        when x"3C" => return x"55";--U
        when x"2A" => return x"56";--V
        when x"1D" => return x"57";--W
        when x"22" => return x"58";--X
        when x"35" => return x"59";--Y
        when x"1A" => return x"5A";--Z
		  when x"00" => return x"EF";
		  when x"FF" => return x"FC";
        when others => return x"FF";
    end case;
end decoding;
--
--------------------------------------------------------------------------------------
--
--Start of circuit description.
--
begin
    --
    --Indicating the arriving of the data.
    DATA_ARV <= scan_data_arv;
    ----------------------------------------------------------------------------------------
    --
    --Deviding the input clock(50MHz) into 1MHz.
    --
    clk_divide_10: process(CLK_IN)
    begin
        if rising_edge(CLK_IN) then
            if clk_cnt1 = "110001" then
                clk_cnt1 <= "000000";
                clk <= not clk;
            else
                clk_cnt1 <= clk_cnt1 + 1;
            end if;
        end if;
    end process clk_divide_10; 
    --
    clk_divide_4: process(CLK_IN)
    begin
        if rising_edge(CLK_IN) then
            if div_4 = "11" then
                div_4 <= "00";
                clk_uart <= not clk_uart;
            else
                div_4 <= div_4 + 1;
            end if;
        end if;
    end process clk_divide_4;
    --------------------------------------------------------------------------------------
    --
    --Detecting the falling edge of the PS2 clock.
    --
    --Filtering the raw clock signal coming from the keyboard,
    --8 successive '1's or '0's makes the ps2_st change.
    --Synchronizing with the "clk"(1MHz). 
    --
    edge_dtct: process (clk, RST)
    begin
        if RST = '1' then
            PS2_datr <= '0';
            PS2_clk_f <= '0';
            filter <= (others=>'0');
            fall_clk <= '0';
        elsif rising_edge (clk) then
            PS2_datr <= PS2_DATA;
            fall_clk <= '0';
            filter <= PS2_CLK  & filter(7 downto 1);
            if filter = "11111111" then
                PS2_clk_f <= '1';
            elsif filter = "00000000" then
                PS2_clk_f <= '0';
                if PS2_clk_f = '1' then
                    fall_clk <= '1';
                end if;
            end if;
        end if;
    end process edge_dtct;
    --------------------------------------------------------------------------------------
    --
    --Receiving the data from the keyboard,and do the parity checking. 
    --
    ps2_data_rcv: process(clk, RST)
    begin
        if RST = '1' then
            ps2_st <= ps2_idle;
            data_pstn <= (others => '0');
            shift_reg <= (others => '0');
            kbd_data <= (others => '0');
            parity <= '0';
            scan_data_arv <= '0';
            ERR_IND <= '0';
        elsif rising_edge (clk) then
            case ps2_st is
                when ps2_idle =>
                    parity <= '0';
                    data_pstn <= (others => '0');
                    if fall_clk='1' and PS2_datr='0' then --Start bit
                        ERR_IND <= '0';
                        ps2_st <= ps2_shifting;
                    end if;
                when ps2_shifting =>
                    if data_pstn >= 9 then
                        if fall_clk='1' then --Stop Bit
                        --Error is (wrong Parity) or (Stop='0') or Overflow
                            ERR_IND <= (not parity) or (not PS2_datr) or scan_data_arv;
                            scan_data_arv <= '1';
                            kbd_data <= shift_reg(7 downto 0);
                            ps2_st <= ps2_idle;
                            data_pstn <= (others => '0');
                        end if;
                    elsif fall_clk='1' then
                        data_pstn <= data_pstn + 1;
                        shift_reg <= PS2_datr & shift_reg(8 downto 1);--Shift right
                        parity <= parity xor PS2_datr;
                    end if;
                when others =>--Never reached
                    ps2_st <= ps2_idle;
            end case;
        end if;
    end process ps2_data_rcv;
    ------------------------------------------------------------------------------------
    --
    --Generating the baud rate used for transmiting.
    --
    --///*******************************************************************////
    tx_baud_rate_gen: process(RST, CLK_IN, BDRx16)