bzq.vhd

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bzq is
 port(bena:in std_logic;
      bclk:in std_logic;
      clr:in std_logic;
      bzq:buffer std_logic_vector(31 downto 0));
end bzq;
architecture behav of bzq is
begin
 process(clr,bclk)
  begin
     if clr='1' then bzq<=(others=>'0');
     else 
         if bena='1' then bzq<=bzq+1;
         end if;
     end if;
  end process;
end behav;