img.vhd

FPGA做VGA通讯的详细资料

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity img is
	port(clk50mhz:in std_logic;
		hs,vs,r,g,b:out std_logic);
end img;
architecture behave of img is
	component vga640480
		port(clk:in std_logic;
			rgbin:in std_logic_vector(2 downto 0);
			hs,vs,r,g,b:out std_logic;
			hcntout,vcntout:out std_logic_vector(9 downto 0));
	end component;
	component imgrom
		port(inclk:in std_logic;
			address:out std_logic_vector(19 downto 0);
			q:out std_logic_vector(2 downto 0));
	end component;
	signal rgb:std_logic_vector(2 downto 0);
	signal clk25mhz:std_logic;
	signal romaddr:std_logic_vector(19 downto 0);
	signal hpos,vpos:std_logic_vector(9 downto 0);
begin
	romaddr<=vpos(9 downto 0)& hpos(9 downto 0);
	process(clk50mhz)
	begin
		if(clk50mhz' event and clk50mhz ='1')then clk25mhz<=not clk25mhz;
		end if;
	end process;
	i_vga640480:vga640480 port map(clk=>clk25mhz,rgbin=>rgb,hs=>hs,
		vs=>vs,r=>r,g=>g,b=>b,hcntout=>hpos,vcntout=>vpos);
	i_rom:imgrom port map(inclk=>clk25mhz,address=>romaddr,q=>rgb);
end behave;