vga640480.vhd

来自「FPGA做VGA通讯的详细资料」· VHDL 代码 · 共 59 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity vga640480 is
	port(clk:in std_logic;
		hs,vs,r,g,b:out std_logic;
		rgbin:in std_logic_vector(2 downto 0);
		hcntout,vcntout:out std_logic_vector(9 downto 0));
end vga640480;

architecture behave of vga640480 is
	signal hcnt,vcnt:std_logic_vector(9 downto 0);
begin
	hcntout<=hcnt;
	vcntout<=vcnt;
	ProA:process(clk)
	begin
		if(rising_edge(clk))then
			if(hcnt <800)then hcnt<=hcnt+1;
			else hcnt<=(others=>'0');
			end if;
		end if;
	end process;
	ProB:process(clk)
	begin
		if(rising_edge(clk))then
			if(hcnt <640+8)then 
				if(vcnt<525)then vcnt<=vcnt+1;
				else vcnt<=(others=>'0');
				end if;
			end if;
		end if;
	end process;
	ProC:process(clk)
	begin
		if(rising_edge(clk))then
			if((hcnt >=640+8+8)and (hcnt<640+8+8+96))then hs<='0';
			else hs<='1';
			end if;
		end if;
	end process;
	ProD:process(vcnt)
	begin
		if((vcnt >=480+8+2)and (vcnt<480+8+2+2))then vs<='0';
		else vs<='1';
		end if;
	end process;
	ProE:process(clk)
	begin
		if(rising_edge(clk))then
			if(hcnt<640 and vcnt<480)then
				r<=rgbin(2);g<=rgbin(1);b<=rgbin(0);
			else
				r<='0';g<='0';b<='0';
			end if;
		end if;
	end process;
end behave;