tf.vhd

等精度数字频率计 的一个工程---包括vhdl源程序和编译后产生的相关文件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity tf is 
 port(ena:in std_logic;
      tclk:in std_logic;
      clr:in std_logic;
      tsq:buffer std_logic_vector(31 downto 0));
end tf;
architecture behav of tf is
begin
 process(clr,tclk)
  begin
    if clr='1' then tsq<=(others=>'0');
    else 
      if tclk'event and tclk='1' then
         tsq<=tsq+1;
      end if;
    end if;
  end process; 
end behav;