代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/385315/8809612
txt 移位寄存器.txt
--4位移位寄存器
--DIR:控制方向,高电平向右
--CLK:时钟端,高电平触发
--CLR:同步清零端,高电平触发
--SET:同步置位端,高电平触发
--LOAD:高电平触发,保存数据
--CE:时钟控制端,高电平有效
-------------------------------------------------------------------------------
www.eeworm.com/read/385313/8809632
txt 移位寄存器.txt
--4位移位寄存器
--DIR:控制方向,高电平向右
--CLK:时钟端,高电平触发
--CLR:同步清零端,高电平触发
--SET:同步置位端,高电平触发
--LOAD:高电平触发,保存数据
--CE:时钟控制端,高电平有效
-------------------------------------------------------------------------------
www.eeworm.com/read/385306/8809657
txt 7bjq.txt
要求用VHDL语言设计7人表决器电路，了解变量和信号的区别，了解进程内部顺序语句及外部并行语句的区别。library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY vote7 IS
PORT
( men: IN std_logic_vector(6 do
www.eeworm.com/read/428962/8826706
vhd testcnt.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity testcnt is
end entity testcnt;
architecture io of testcnt is
signal clk: std_logic := '0';
signal rst: std_logic := '1';
signal st:
www.eeworm.com/read/384817/8842378
vhd shizhong.vhd
Library Ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shizhong is
port(
inclk : in std_logic;
set :in std_logic;
mode :in std_logic;
outa :out
www.eeworm.com/read/384728/8849378
vhd 53_counter.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package mycntpkg is
component count port(clk,rst : in std_logic;
cnt : inout std_logic_vector(2 downto 0));
end component;
end mycntpkg;
www.eeworm.com/read/428603/8856532
vhd topdesign.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
------------------------------------------------------
entity Design
www.eeworm.com/read/428603/8856547
vhd vga_interface.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Vga_interface is
Port ( clk : in STD_LOGIC;
HS : out STD_LOGIC;
VS : out STD_LOGIC;
www.eeworm.com/read/428603/8856551
vhd comrx.vhd
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
entity ComRx is
port ( clk : in std_logic;
din :
www.eeworm.com/read/428599/8856633
vhd vga.vhd
-------------------------------------------------------------------------------
-- vga.vhd
--
-- Author(s): Ashley Partis and Jorgen Peddersen
-- Created: Jan 2001
-- Last Modified: Jan