comrx.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;

entity  ComRx is
    port (  clk : in  std_logic;			   
			   din : in std_logic;
				Red_out : out std_logic;
				Green_out : out std_logic;
				Blue_out : out std_logic;
				hs_out : out std_logic;
				vs_out : out std_logic;
				Bytesc1: out std_logic_vector(7 downto 0);
				byteOut: out std_logic_vector(7 downto 0));   
end  ComRx;

architecture a of ComRx is
	Component divclk_5k
		 Port ( clk0 : in  STD_LOGIC;
				  clk1 : out STD_LOGIC);
	end component;		  
	
	Component decodeSctoled 
    Port ( 	scancode : in  STD_LOGIC_VECTOR (7 downto 0);
    		disptoled : out  STD_LOGIC_VECTOR (7 downto 0));
	end component;	
	
	Component VGA_Rx 
    Port ( clk50_in : in std_logic;
			sc : in std_logic_vector(7 downto 0);			
           Red_out : out std_logic;
           Green_out : out std_logic;
           Blue_out : out std_logic;
           hs_out : out std_logic;
           vs_out : out std_logic);
	end component;	
	
	type state_type is (idle, RxBit);
   signal state : state_type;
	signal cnt1:  std_logic_vector(4 downto 0);
	signal Bytesc : std_logic_vector(7 downto 0);
	signal clk5 : std_logic;
	
begin  
	B2: divclk_5k port map (clk,clk5);
	B5: decodeSctoled  port map (Bytesc,byteOut);
	B6: VGA_Rx port map (clk,Bytesc,Red_out,Green_out,Blue_out,hs_out,vs_out);
 process (clk5)
   -- variables change value imediately
   variable index : integer range 0 to 10;
   variable reg : std_logic_vector(10 downto 0):= (others => '1');
begin  -- process   
   if(clk5'event and clk5 = '1')then
   		case state is
	        when idle => 
		         if (reg(0)='1' and din='0') then
						state <= RxBit; 
						reg(0):='0';
		      	else 
			        	state <= idle; 
			         index := 0;	
						reg := (reg'range => '1');		
		        	end if;             
	        when RxBit =>
	          	index := index + 1;
	          	if (index < 10) then
			          	state <= RxBit;		          	
			          	reg(index):= din;
	          	elsif(index = 10) then
			            state <= idle; 
			            index := 0;
			            reg(0):= din; 
			            Bytesc( 7 downto 0) <= reg( 8 downto 1);							
							Bytesc1 <= Bytesc;
--							if cnt1 < "10100" then
--								cnt1<= cnt1 + 1;
--							else
--								cnt1 <= "00001";
--							end if;
					end if;
      end case;
--		cnt <= cnt1;		
   end if;			        
  end process;
end a;