vga_interface.vhd

many application on kit SP-3: VGA, digital clock, counter, interface PS2....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Vga_interface is
 Port ( clk : in STD_LOGIC;
 HS : out STD_LOGIC;
 VS : out STD_LOGIC;
 X : out std_logic_vector (9 downto 0);
 Y : out std_logic_vector (9 downto 0);
 Blank : out std_logic);
end Vga_interface;

architecture Behavioral of Vga_interface is

------- signals declarations
signal clk25 : std_logic;
signal Hcount : std_logic_vector(9 downto 0);
signal Vcount : std_logic_vector(9 downto 0);
begin
-- generate a 25Mhz clock
divide_by_two_counter:process (clk)
  	begin
   		if clk'event and clk='1' then
				clk25 <= not clk25;
			end if;
		end process;

HS_VS_generator :process (clk25)
begin
if clk25'event and clk25='1' then
				Hcount<= Hcount + 1;
				if (Hcount = 800)then
					Hcount <= "0000000000";
					Vcount <= Vcount + 1;
				end if;
			if (Vcount = 521)then
				Vcount <= "0000000000";
			end if;

	if (Hcount >=144 and Hcount < 783 
				and Vcount >=31 and Vcount <510) then
		Blank <='1';
	else
		Blank <='0';
	end if;

	if (Hcount < 96)then
		HS <= '0';
	else
		HS <= '1';
	end if;

	if (Vcount < 2)then
		VS <= '0';
	else
		VS <= '1';
	end if;
end if;
end process;
	X <= Hcount - 144;
	Y <= Vcount - 31;
end Behavioral;