代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/438140/7735867
vhd main_control.vhd
------------------------------------------------------------------------------
-- Project : Video Capture Control
-- Programmer : Byungchan Son
-- Function : Main Control - 傈眉 葛碘 力绢, 鸥捞怪 炼沥
--
www.eeworm.com/read/485365/6560008
vhd acs_unit.vhd
-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
-
www.eeworm.com/read/485373/6560559
vhd acs_unit.vhd
-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
-
www.eeworm.com/read/485378/6560781
vhd acs_unit.vhd
-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
-
www.eeworm.com/read/485425/6561672
vhd spwm.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:32 04/17/2009
-- Design Name:
-- Module Name: SPWM - RTL
www.eeworm.com/read/483725/6592420
vhd lab3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab3 is
port( S2S1S0 : IN std_logic_vector(2 downto 0);
A1 :in std_logic_vector(3 downto 0);
B1
www.eeworm.com/read/483725/6592421
txt dfgadg.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab3 is
port( S2S1S0 : IN std_logic_vector(2 downto 0);
A1 :in std_logic_vector(3 downto 0);
B1
www.eeworm.com/read/478303/6714511
vhd ex_p4_28_bcd_add.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BCD_ADDER is
port (A,B:in std_logic_VECTOR(3 downto 0);
S: out std_logic_VECTOR(3 downto 0);
Cin : in
www.eeworm.com/read/158164/11639967
vhd tx_inter.vhd
-- ************************************************************************
-- ** REFERENCE DESIGN PART-1 **
-- *******************************************
www.eeworm.com/read/267115/11193441
lst cy4623_rdk.lst
0000: 7D 00 68 LJMP 0x0068
0003: 30 HALT
FILE: .\boot.asm
(0001) ; Generated by PSoC Designer ver 4.2 b1013 : 02 September, 2004