tx_inter.vhd

Convolutional Interleaver Encoder

-- ************************************************************************
-- **                     REFERENCE DESIGN PART-1                        **
-- ************************************************************************

-- ************************************************************************
-- **          Convolutional Interleaver with B=32 delay stages          **
-- ************************************************************************ 
-- **  This code will make use of components SRL16 to implement the      **
-- **  progressive delay line.                                           **
-- **  SRL16 is an exclusive feature of Virtex architecture (Virtex-E,   **
-- **  Virtex, Spartan-2) that allows YOU to save a lot of room and      **
-- **  increase tremendously YOUR performance.                           **
-- ************************************************************************

-- ******************************************************
-- **  Authors: Gianluca Gilardi - Xilinx Italy        ** 
-- **           Catello Antonio De Rosa - Siemens-ICN  **
-- **  Date:    July 2000                              **
-- ****************************************************** 
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

-- Synopsys translate_off
 Library UNISIM;
 use UNISIM.all;
-- Synopsys translate_on


entity TX_INTER is
    port(
     	CLK	: In    std_logic;	-- system clock
        RESET	: In    std_logic;	-- system reset
        SIN	: In    std_logic;	-- serial data input
        SYNC_TX	: In    std_logic;	-- input TX synchronism
        SOUT	: Out   std_logic	-- serial data output
     );	
end TX_INTER;

architecture BEHAVIORAL of TX_INTER is

signal DATA_IN	  : std_logic_vector(0 to 31); -- input SIPO
signal DATA_OUT	  : std_logic_vector(0 to 31); -- delay element output data vector
signal DATA_SHIFT : std_logic_vector(0 to 31); -- output PISO

type MATRIX is array (1 to 31) of unsigned(4 downto 0);
signal A : MATRIX;
signal DATA_MSB: std_logic_vector(17 to 31);
signal logic1: std_logic;

component SRL16E
  port (D   : in STD_ULOGIC;
        CE  : in STD_ULOGIC;
        CLK : in STD_ULOGIC;
        A0  : in STD_ULOGIC;
        A1  : in STD_ULOGIC;
        A2  : in STD_ULOGIC;
        A3  : in STD_ULOGIC;
        Q   : out STD_ULOGIC);
end component;


begin

logic1<= '1';

-- Following SIPO (Serial In Parallel Out) is implemented with Flip Flops
-- Another solution is to use Block RAMs if not needed for other parts
SIPO_ELEMENT: process(RESET,CLK) begin
	if (RESET='1') then
	  DATA_IN<=(others=>'0');
	elsif (CLK'event and CLK='1') then
    	  DATA_IN(0)<=SIN;
    	  for I in 1 to 31 loop
           DATA_IN(I)<=DATA_IN(I-1);
    	  end loop;
	end if;
end process SIPO_ELEMENT;

DATA_OUT(0)<=DATA_IN(0);

-- DELAYS_LSB will instantiate one SRL16 per line from 1 to 16 
-- delay units.
DELAYS_LSB: for I in 1 to 16 generate
	    A(I)<= conv_unsigned(I-1,5);
	    DE_1: SRL16E
	     port map (
	       D=>DATA_IN(I),
	       CE=>SYNC_TX,CLK=>CLK,
	       A0=>A(I)(0),A1=>A(I)(1),
	       A2=>A(I)(2),
	       A3=>A(I)(3),
	       Q=>DATA_OUT(I));
end generate;

-- DELAYS_MSB will instantiate two SRL16 per line from 17 to 31 
-- delay units.
DELAYS_MSB: for I in 17 to 31 generate
	    A(I)<= conv_unsigned(I-1,5);
	    DE_2: SRL16E
	     port map (
	       D=>DATA_IN(I),
	       CE=>SYNC_TX,CLK=>CLK,
	       A0=>logic1,
	       A1=>logic1,
	       A2=>logic1,
	       A3=>logic1,
	       Q=>DATA_MSB(I));
	    DE_3: SRL16E 
	     port map (
	       D=>DATA_MSB(I),
	       CE=>SYNC_TX,
	       CLK=>CLK,
	       A0=>A(I)(0),
	       A1=>A(I)(1),
	       A2=>A(I)(2),
	       A3=>A(I)(3),
	       Q=>DATA_OUT(I));
end generate;

-- Following PISO (Parallel In Serial Out) is implemented with Flip Flops
-- Another solution is to use Block RAMs if not needed for other parts
PISO_ELEMENT:process(RESET,CLK) begin
	if (RESET='1') then
	  DATA_SHIFT<=(others=>'0');
	elsif (CLK'event and CLK='1') then
    	  if (SYNC_TX='1') then
            DATA_SHIFT<= DATA_OUT;
    	  else
	    for I in 31 downto 1 loop
             DATA_SHIFT(I)<=DATA_SHIFT(I-1);
            end loop;
    	  end if;
	end if;
end process PISO_ELEMENT;

SOUT<= DATA_SHIFT(31);

end BEHAVIORAL;