acs_unit.vhd

这是一个计算维特比译码的程序

-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
--
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.viterbi_block_pkg.ALL;

ENTITY ACS_Unit IS
  PORT( clk                               :   IN    std_logic;
        reset                             :   IN    std_logic;
        enb                               :   IN    std_logic;
        In1                               :   IN    vector_of_std_logic_vector4(0 TO 3);   
        Out1                              :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
        Out2                              :   OUT   std_logic_vector(7 DOWNTO 0)   
        );
END ACS_Unit;


ARCHITECTURE rtl OF ACS_Unit IS

  -- Component Declarations
  COMPONENT Reorder
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          IN_1                            :   IN    vector_of_std_logic_vector4(0 TO 63);   
          OUT_1                           :   OUT   vector_of_std_logic_vector4(0 TO 63)    
          );
  END COMPONENT;

  COMPONENT Renormalize
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          In1                             :   IN    vector_of_std_logic_vector4(0 TO 63);   
          IDX                             :   OUT   std_logic_vector(7 DOWNTO 0);  
          SM                              :   OUT   vector_of_std_logic_vector4(0 TO 63)    
          );
  END COMPONENT;

  COMPONENT ACS
    PORT( clk                             :   IN    std_logic;
          reset                           :   IN    std_logic;
          enb                             :   IN    std_logic;
          BM                              :   IN    vector_of_std_logic_vector4(0 TO 3);    
          SM                              :   IN    vector_of_std_logic_vector4(0 TO 63);   
          DEC                             :   OUT   std_logic_vector(0 TO 63);  -- boolean [64]
          NSM                             :   OUT   vector_of_std_logic_vector4(0 TO 63)    
          );
  END COMPONENT;

  -- Component Configuration Statements
  FOR ALL : Reorder
    USE ENTITY work.Reorder(rtl);

  FOR ALL : Renormalize
    USE ENTITY work.Renormalize(rtl);

  FOR ALL : ACS
    USE ENTITY work.ACS(rtl);

  -- Local Type Definitions
  TYPE vector_of_unsigned4 IS ARRAY (NATURAL RANGE <>) OF unsigned(3 DOWNTO 0);

  -- Signals
  SIGNAL ACS_out2                         : vector_of_std_logic_vector4(0 TO 63);    
  SIGNAL Reorder_out1                     : vector_of_std_logic_vector4(0 TO 63);    
  SIGNAL Renormalize_out1                 : std_logic_vector(7 DOWNTO 0);  
  SIGNAL Renormalize_out2                 : vector_of_std_logic_vector4(0 TO 63);    
  SIGNAL s                                : vector_of_unsigned4(0 TO 63);    
  SIGNAL Store_State_Metrics_out1         : vector_of_unsigned4(0 TO 63);    
  SIGNAL s_1                              : vector_of_std_logic_vector4(0 TO 63);    
  SIGNAL ACS_out1                         : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL Selector_out1                    : std_logic_vector(0 TO 63);  -- boolean [64]
  SIGNAL s_2                              : unsigned(7 DOWNTO 0);  -- uint32
  SIGNAL Data_Type_Conversion_out1        : unsigned(7 DOWNTO 0);  -- uint8

BEGIN
  u_Reorder : Reorder
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       IN_1 => ACS_out2,    
       OUT_1 => Reorder_out1    
       );

  u_Renormalize : Renormalize
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       In1 => Reorder_out1,    
       IDX => Renormalize_out1,  
       SM => Renormalize_out2    
       );

  u_ACS : ACS
    PORT MAP
      (clk => clk,
       reset => reset,
       enb => enb,
       BM => In1,    
       SM => s_1,    
       DEC => ACS_out1,  -- boolean 
       NSM => ACS_out2    
       );
  outputgen1: FOR k IN 0 TO 63 GENERATE
    s(k) <= unsigned(Renormalize_out2(k));
  END GENERATE;

  Store_State_Metrics_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Store_State_Metrics_out1 <= (OTHERS => (OTHERS => '0'));
    ELSIF clk'event AND clk = '1' THEN
      IF enb = '1' THEN
        Store_State_Metrics_out1(0 TO 63) <= s(0 TO 63);
      END IF;
    END IF; 
  END PROCESS Store_State_Metrics_process;


  outputgen: FOR k IN 0 TO 63 GENERATE
    s_1(k) <= std_logic_vector(Store_State_Metrics_out1(k));
  END GENERATE;

  Selector_out1(0) <= ACS_out1(0);
  Selector_out1(1) <= ACS_out1(2);
  Selector_out1(2) <= ACS_out1(4);
  Selector_out1(3) <= ACS_out1(6);
  Selector_out1(4) <= ACS_out1(8);
  Selector_out1(5) <= ACS_out1(10);
  Selector_out1(6) <= ACS_out1(12);
  Selector_out1(7) <= ACS_out1(14);
  Selector_out1(8) <= ACS_out1(16);
  Selector_out1(9) <= ACS_out1(18);
  Selector_out1(10) <= ACS_out1(20);
  Selector_out1(11) <= ACS_out1(22);
  Selector_out1(12) <= ACS_out1(24);
  Selector_out1(13) <= ACS_out1(26);
  Selector_out1(14) <= ACS_out1(28);
  Selector_out1(15) <= ACS_out1(30);
  Selector_out1(16) <= ACS_out1(32);
  Selector_out1(17) <= ACS_out1(34);
  Selector_out1(18) <= ACS_out1(36);
  Selector_out1(19) <= ACS_out1(38);
  Selector_out1(20) <= ACS_out1(40);
  Selector_out1(21) <= ACS_out1(42);
  Selector_out1(22) <= ACS_out1(44);
  Selector_out1(23) <= ACS_out1(46);
  Selector_out1(24) <= ACS_out1(48);
  Selector_out1(25) <= ACS_out1(50);
  Selector_out1(26) <= ACS_out1(52);
  Selector_out1(27) <= ACS_out1(54);
  Selector_out1(28) <= ACS_out1(56);
  Selector_out1(29) <= ACS_out1(58);
  Selector_out1(30) <= ACS_out1(60);
  Selector_out1(31) <= ACS_out1(62);
  Selector_out1(32) <= ACS_out1(1);
  Selector_out1(33) <= ACS_out1(3);
  Selector_out1(34) <= ACS_out1(5);
  Selector_out1(35) <= ACS_out1(7);
  Selector_out1(36) <= ACS_out1(9);
  Selector_out1(37) <= ACS_out1(11);
  Selector_out1(38) <= ACS_out1(13);
  Selector_out1(39) <= ACS_out1(15);
  Selector_out1(40) <= ACS_out1(17);
  Selector_out1(41) <= ACS_out1(19);
  Selector_out1(42) <= ACS_out1(21);
  Selector_out1(43) <= ACS_out1(23);
  Selector_out1(44) <= ACS_out1(25);
  Selector_out1(45) <= ACS_out1(27);
  Selector_out1(46) <= ACS_out1(29);
  Selector_out1(47) <= ACS_out1(31);
  Selector_out1(48) <= ACS_out1(33);
  Selector_out1(49) <= ACS_out1(35);
  Selector_out1(50) <= ACS_out1(37);
  Selector_out1(51) <= ACS_out1(39);
  Selector_out1(52) <= ACS_out1(41);
  Selector_out1(53) <= ACS_out1(43);
  Selector_out1(54) <= ACS_out1(45);
  Selector_out1(55) <= ACS_out1(47);
  Selector_out1(56) <= ACS_out1(49);
  Selector_out1(57) <= ACS_out1(51);
  Selector_out1(58) <= ACS_out1(53);
  Selector_out1(59) <= ACS_out1(55);
  Selector_out1(60) <= ACS_out1(57);
  Selector_out1(61) <= ACS_out1(59);
  Selector_out1(62) <= ACS_out1(61);
  Selector_out1(63) <= ACS_out1(63);



  Out1 <= Selector_out1;

  s_2 <= unsigned(Renormalize_out1);

  Data_Type_Conversion_out1 <= s_2(7 DOWNTO 0);


  Out2 <= std_logic_vector(Data_Type_Conversion_out1);

END rtl;