spwm.vhd

VHDL实现 SPWM 通过ADC1407转换实现变频控制和变幅控制； 通过LCD1602实现频率和调制比显示

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    14:06:32 04/17/2009 
-- Design Name: 
-- Module Name:    SPWM - RTL 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SPWM is
    Port ( CLK : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
			  PUT_HZ:in integer range 0 to 255;
			  PUT_ff:in integer range 0 to 255;
  			  A1_RESULT : out  STD_LOGIC;
           A2_RESULT : out  STD_LOGIC;
			  B1_RESULT : out  STD_LOGIC;
           B2_RESULT : out  STD_LOGIC;
			  C1_RESULT : out  STD_LOGIC;
           C2_RESULT : out  STD_LOGIC);
end SPWM;

architecture RTL of SPWM is


	COMPONENT ZXIANBO
	PORT(
		CLK : IN std_logic;
		RESET : IN std_logic;
	   PUT_HZ:in integer range 0 to 255;
	   PUT_ff:in integer range 0 to 255;    
		A_Adjust : OUT std_logic_vector(7 downto 0);
		B_Adjust : OUT std_logic_vector(7 downto 0);
		C_Adjust : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

  COMPONENT SANJIAOBO
	PORT(
		CLK : IN std_logic;
		RESET : IN std_logic;
		PUT_HZ : IN integer range 0 to 255;
		SANJIAO_DATA : OUT std_logic_vector(7 downto 0)
		);
  END COMPONENT;

	COMPONENT COMP
	PORT(
		CLK : IN std_logic;
		RESET : IN std_logic;
		SANJIAO_DATA : IN std_logic_vector(7 downto 0);
		A_Adjust : IN std_logic_vector(7 downto 0);
		B_Adjust : IN std_logic_vector(7 downto 0);
		C_Adjust : IN std_logic_vector(7 downto 0);          
		A1_RESULT : OUT std_logic;
		A2_RESULT : OUT std_logic;
		B1_RESULT : OUT std_logic;
		B2_RESULT : OUT std_logic;
		C1_RESULT : OUT std_logic;
		C2_RESULT : OUT std_logic
		);
	END COMPONENT;

signal SANJIAO_DATA:STD_LOGIC_VECTOR (7 downto 0);
signal A_Adjust: STD_LOGIC_VECTOR (7 downto 0);
signal B_Adjust: STD_LOGIC_VECTOR (7 downto 0);
signal C_Adjust: STD_LOGIC_VECTOR (7 downto 0);

begin
	
	Inst_ZXIANBO: ZXIANBO PORT MAP(
		CLK => CLK,
		RESET => RESET,
		PUT_HZ => PUT_HZ,
		PUT_ff => PUT_ff,
		A_Adjust => A_Adjust,
		B_Adjust => B_Adjust,
		C_Adjust => C_Adjust
	);
	
	Inst_SANJIAOBO: SANJIAOBO PORT MAP(
		CLK => CLK,
		RESET => RESET,
		PUT_HZ => PUT_HZ,
		SANJIAO_DATA => SANJIAO_DATA
	);


	Inst_COMP: COMP PORT MAP(
		CLK => CLK,
		RESET => RESET,
		SANJIAO_DATA => SANJIAO_DATA ,
		A_Adjust => A_Adjust,
		B_Adjust => B_Adjust,
		C_Adjust => C_Adjust,
		A1_RESULT => A1_RESULT ,
		A2_RESULT => A2_RESULT,
		B1_RESULT => B1_RESULT,
		B2_RESULT => B2_RESULT,
		C1_RESULT => C1_RESULT,
		C2_RESULT => C2_RESULT
	);

end RTL;