main_control.vhd

infra pen controller, cmos sensor control and sdram control

------------------------------------------------------------------------------
-- Project 		: Video Capture Control
-- Programmer	: Byungchan Son
-- Function		: Main Control - 傈眉 葛碘 力绢, 鸥捞怪 炼沥
-- Language		: VHDL
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity main_control is
	port(
		-- system signal
		reset : in std_logic;
		clock : in std_logic;
		-- video control signal
		video_control_command : out std_logic_vector(2 downto 0);
			-- 000 : display camera data
			-- 001 : capture camera data
			-- 010 : display capture data
		capture_end_sta : in std_logic;
		capture_end_ack : out std_logic;
		vsync_start : in std_logic;
		hsync_start : in std_logic;
		-- sdram control signal
		sdram_control_command : out std_logic_vector(2 downto 0);
		page_number : out std_logic_vector(5 downto 0);
		page_select_out : out std_logic;
		screen_mode_out : out std_logic_vector(1 downto 0);
			-- 0 : 4 separated screen
			-- 1 : 9 separated screen
		make_screen_end_sta : in std_logic;
		make_screen_end_ack : out std_logic;
		page_current : in std_logic_vector(5 downto 0);
		page_first : out std_logic_vector(5 downto 0);
		page_previous : out std_logic_vector(5 downto 0);
		page_next : out std_logic_vector(5 downto 0);
		-- command receive signal
		capture_command : in std_logic_vector(11 downto 0)
		-- test signal
		);
end main_control;

architecture main_control_a of main_control is

component page_memory
	port(
		address		: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
		);
end component;

type main_control_state is(
	idle,
	capture_exec,
	display_capture,
	make_screen,
	vsync_return,
	hsync_return
	);
type page_state is(
	idle,
	page_read_ready,
	page_read,
	page_read_delay,
	page_display,
	page_check,
	page_valid,
	page_valid_delay,
	page_arrange_ready,
	page_arrange,
	page_arrange_delay,
	page_arrange1,
	page_arrange1_delay,
	page_arrange2,
	page_arrange2_delay
	);
-- state machine signal
signal current_state, next_state : main_control_state;
signal page_current_state, page_next_state : page_state;

-- data signal
signal capture_page : std_logic_vector(4 downto 0);
signal sync_count : std_logic_vector(7 downto 0);
signal screen_mode : std_logic_vector(1 downto 0);
signal page_screen_mode : std_logic_vector(1 downto 0);
	-- 00 : full screen
	-- 01 : 4 separated screen
	-- 10 : 9 separated screen
signal page_select : std_logic;
signal display_flag : std_logic;
-- page renaming
signal display_page1 : std_logic_vector(5 downto 0);
signal display_page2 : std_logic_vector(5 downto 0);
signal display_page3 : std_logic_vector(5 downto 0);
signal display_page4 : std_logic_vector(5 downto 0);
signal display_page5 : std_logic_vector(5 downto 0);
signal display_page6 : std_logic_vector(5 downto 0);
signal display_page7 : std_logic_vector(5 downto 0);
signal display_page8 : std_logic_vector(5 downto 0);
signal display_page9 : std_logic_vector(5 downto 0);
signal temp_page : std_logic_vector(5 downto 0);
signal temp1_page : std_logic_vector(5 downto 0);
signal page_count : std_logic_vector(3 downto 0);
-- page memory
signal address	: STD_LOGIC_VECTOR (4 DOWNTO 0);
signal data		: STD_LOGIC_VECTOR (7 DOWNTO 0);
signal wren		: STD_LOGIC ;
signal q		: STD_LOGIC_VECTOR (7 DOWNTO 0);

begin
	m1 : page_memory
	port map(
		address => address,
		clock => clock,
		data => data,
		wren => wren,
		q => q
		);
	------------------------------------------------------
	-- precess main control
	------------------------------------------------------
	Process_main : process(
		reset,
		clock,
		current_state,
		next_state,
		capture_command,
		capture_page,
		page_select,
		capture_end_sta,
		screen_mode
		)
	begin
		if(reset = '1')then
			-- stste mschine
			next_state <= idle;
			-- video control signal
			video_control_command <= "000";
			capture_end_ack <= '0';
			-- sdram control signal
			sdram_control_command <= "000";
			screen_mode <= "00";
			-- internal signal
			capture_page <= (others => '0');
			sync_count <= (others => '0');
			make_screen_end_ack <= '0';
			page_select <= '0';
			screen_mode <= "00";
			display_flag <= '0';
		elsif(clock'event and clock = '1')then
			case current_state is
				when idle =>
				when capture_exec =>
				when display_capture =>
				when make_screen =>
				when vsync_return =>
				when hsync_return =>
			end case;
		end if;
		current_state <= next_state;
		screen_mode_out <= screen_mode;
		page_select_out <= page_select;
	end process;
	------------------------------------------------------
	-- process page compute
	------------------------------------------------------
	Process_page : process(
		reset,
		clock,
		capture_command,
		screen_mode,
		page_current_state,
		page_next_state
		)
	begin
		if(reset = '1')then
			-- stste mschine
			page_next_state <= idle;
			-- video control signal
			-- sdram control signal
			-- internal signal
			display_page1 <= (others => '0'); 
			display_page2 <= (others => '0'); 
			display_page3 <= (others => '0'); 
			display_page4 <= (others => '0'); 
			display_page5 <= (others => '0'); 
			display_page6 <= (others => '0'); 
			display_page7 <= (others => '0'); 
			display_page8 <= (others => '0'); 
			display_page9 <= (others => '0'); 
			temp_page <= (others => '0'); 
			temp1_page <= (others => '0'); 
			page_count <= (others => '0'); 
			page_first  <= (others => '0');
			page_next  <= (others => '0');
			page_previous  <= (others => '0');
			page_screen_mode  <= "00";
			page_number <= (others => '0');
		elsif(clock'event and clock = '1')then
			case page_current_state is
				when idle =>
				when  page_read_ready =>
				when  page_read =>
				when  page_read_delay =>
				when  page_display =>
				when  page_check =>
				when  page_valid =>
				when  page_valid_delay =>
				when  page_arrange_ready =>
				when  page_arrange =>
				when  page_arrange_delay =>
				when  page_arrange1 =>
				when  page_arrange1_delay =>
				when  page_arrange2 =>
				when  page_arrange2_delay =>
			end case;
			page_first <= display_page1;
		end if;
		page_current_state <= page_next_state;
	end process;
end main_control_a;