dfgadg.txt

组合逻辑单元设计电路

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lab3 is
 port( S2S1S0 : IN std_logic_vector(2 downto 0);
       A1 :in std_logic_vector(3 downto 0);
       B1 :in std_logic_vector(3 downto 0);
       C0 :in std_logic;
       F :out std_logic_vector(4 downto 0)
      );
end lab3;
architecture one of lab3 is
 signal A,B :std_logic_vector(4 downto 0);
begin 
 A<='0'&A1;
 B<='0'&B1;
 process(S2S1S0)
begin
 case S2S1S0 IS
      when "000" => F<=A+B+C0;
      when "001" => F<=A-B-C0;
      when "010" => if C0='0' then
                       F<=A-1; else null;
                    end if;
      when "011" => if C0='0' then
                       F<=A+1; else null;
                    end if;
      when "100" => F<=A and B;
      when "101" => F<=A or B;
      when "110" => F<=A xor B;
      when "111" => F<=not A;
  end case;
end process;
end;