ex_p4_28_bcd_add.vhd

This is the course for VHDL programming

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BCD_ADDER is
	port (A,B:in std_logic_VECTOR(3 downto 0);
	      S: out std_logic_VECTOR(3 downto 0);
	      Cin : in std_logic;
	      Cout:out std_logic);
end BCD_ADDER ;
architecture DF of BCD_ADDER  is
	signal C1:std_logic;-- intermediate carry
	signal S_int:std_logic_VECTOR(4 downto 0);
begin
   s_int <= ('0' & A)+ B + Cin;
   C1    <= '1' when ((s_int(4) = '1') or 
                  (s_int > 9)) else
            '0';
   S <= s_int(3 downto 0) when C1 = '0' else
        s_int(3 downto 0) + 6;
end DF;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity BCD_TB is end  BCD_TB;
architecture BEH of BCD_TB is
   signal A,B,S:std_logic_vector(3 downto 0);
   signal Cin,Cout:std_logic;
begin
    BCD:entity work.BCD_ADDER
       port map(A,B,S,Cin,Cout);
    A <= "0011", "0101" after 200 ns;
    B <= "0101", "1001" after 100 ns;
    Cin <= '0', '1' after 100 ns;
end BEH;