key_scan.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 60 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity KEY_SCAN is
	port (CLK,RST:in STD_LOGIC;S:out STD_LOGIC_VECTOR(3 downto 0);
	         R:in  STD_LOGIC_VECTOR(3 downto 0);valid:out STD_LOGIC;
	         KEY_CODE:out STD_LOGIC_VECTOR(3 downto 0));
end KEY_SCAN;
architecture DF of KEY_SCAN is
	signal cnt,RET_CODE: std_logic_vector (1  downto 0 );
	signal cnt_enable: std_logic;
	
begin
	CNT_PROC: process (CLK,RST )
	
	begin
		if RST= '1'  then cnt<="00";
		elsif CLK'event and CLK='1' then 
			if cnt_enable='1' then cnt<=cnt+1;end if;
		end if;
	end process CNT_PROC;
	S<=	"1110" when cnt ="00" else 
		"1101" when cnt ="01" else 
		"1011" when cnt ="10" else 
		"0111" ;
	cnt_enable<= R(0) and R(1) and R(2) and R(3);
	RET_CODE<=	"00" when R(0)='0' else
			"01" when R(1)='0' else
			"10" when R(2)='0' else
			"11" ;
	KEY_CODE<= cnt & RET_CODE;
	valid<= not cnt_enable;

		
end DF;
--TEST BENCH for key scanner
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity TB_KEY is
end TB_KEY;
architecture BEH of TB_KEY is
	signal clk,rst,V:std_logic:='0';
	signal SCAN,K_CODE,RET: std_logic_vector ( 3 downto 0 );

	component KEY_SCAN 
	       port (CLK,RST:in STD_LOGIC;S:out STD_LOGIC_VECTOR(3 downto 0);
	         	R:in  STD_LOGIC_VECTOR(3 downto 0);valid:out STD_LOGIC;
	         	KEY_CODE:out STD_LOGIC_VECTOR(3 downto 0));
	end component;
 begin
	K1:KEY_SCAN port map(clk,rst,SCAN,RET,V,K_CODE);
	rst<='1','0' after 25 ns;
	clk<= not clk after 50 ns;
	RET<="1111","1110" after 400 ns,"1111" after 500 ns,"1101" after 600 ns,
		"1111" after 700 ns,"1011" after 800 ns,"1111" after 1000 ns,
		"0111" after 1100 ns,"1111" after 1300 ns;
end BEH;