ex_p2_17_parity.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 7 行

entity PARITY is
   port (A: in BIT_VECTOR(3 downto 0); P: out BIT);
end PARITY;
architecture A1 of PARITY is
begin
   P <= A(0) xor A(1) xor A(2) xor A(3);
end A1;