ex_p2_15_clock.vhd

来自「This is the course for VHDL programming」· VHDL 代码 · 共 18 行

Entity CLK is end CLK;
Architecture TEST1 of CLK is
    Signal Clock: BIT;
begin
   Clock <= not Clock after 500 ns;
End TEST1;  
Architecture TEST2 of CLK is
Signal Clock: BIT;
begin
   Clock_proc: process
   Begin
		Clock <= '0';
		Wait for 400 ns;
		Clock <= '1';
		Wait for 600 ns;
   End process Clock_proc;
End TEST2;