代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/472423/6867923
vhd encode.vhd
library ieee;
use ieee.std_logic_1164.all;
entity encode is
port(
d: in std_logic_vector(7 downto 0);
ein : in std_logic;
a0n,a1n,a2n,gsn,eon : out std_logic);
end encode;
architecture beh
www.eeworm.com/read/472423/6868016
vhd t10.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t10 IS
PORT(
cpd,cps : IN STD_LOGIC;
lr,lg,ly : OUT STD_LOGIC_VECTOR(4 downto 1);
d : OUT STD_LOGIC_VECTOR(6 downto 0);
sel : OUT STD_
www.eeworm.com/read/472423/6868027
vhd tbjsb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tbjsb IS
PORT(
cp : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(2 downto 0));
END tbjsb;
ARCHITECTURE a OF tbjsb IS
COMPONENT JKFF
PORT (j
www.eeworm.com/read/471796/6882071
vhd list_ch_app_a06.vhd
--*********************************************
-- Listing A.6
--*********************************************
library ieee;
use ieee.std_logic_1164.all;
entity decoder2 is
port(
a: in
www.eeworm.com/read/471796/6882073
vhd list_ch13_08_pong_counter.vhd
-- Listing 13.8
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity m100_counter is
port(
clk, reset: in std_logic;
d_inc, d_clr: in std_logic;
dig
www.eeworm.com/read/471649/6887735
vhd seg7_lut_8_0.vhd
-- SEG7_LUT_8_0.vhd
-- This file was auto-generated as part of a SOPC Builder generate operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all
www.eeworm.com/read/471411/6892442
vhd audiotop.vhd
-------------------------------------------------------------------------------
-- audiotop
--
-- Author(s): James Brennan and Jorgen Peddersen
-- Created: Dec 2000
-- Last Modified: De
www.eeworm.com/read/471411/6892444
vhd remap.vhd
-------------------------------------------------------------------------------
-- remap.vhd
--
-- Created: Dec 2000
-- Last Modified: Dec 2000
--
-- This file only renames signals to nam
www.eeworm.com/read/471200/6899268
vhd uart_clock.vhd
--
-- KCPSM3 reference design - Real Time Clock with UART communications
--
-- Ken Chapman - Xilinx Ltd - October 2003
--
-- The design demonstrates the following:-
-- Connection of KC
www.eeworm.com/read/295206/8180391
vhd lcd1602.vhd
---------------------------------------------------------------------------------------------------
--*************************************************************************************************