t10.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 43 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY t10 IS
	PORT(
		cpd,cps : IN	STD_LOGIC;
		lr,lg,ly : OUT	STD_LOGIC_VECTOR(4 downto 1);
		d : OUT STD_LOGIC_VECTOR(6 downto 0);
		sel : OUT STD_LOGIC_VECTOR(2 downto 0));
END t10;
ARCHITECTURE a OF t10 IS
COMPONENT tbjsa
	PORT(
		cp : IN	STD_LOGIC;
		q : OUT	STD_LOGIC_VECTOR(4 downto 0));
END COMPONENT;
COMPONENT tbjsb
	PORT(
		cp : IN	STD_LOGIC;
		q : OUT	STD_LOGIC_VECTOR(2 downto 0));
END COMPONENT;
COMPONENT dk
	PORT(
		cp : IN STD_LOGIC;
		sj : IN	STD_LOGIC_VECTOR(4 downto 1);
		lr,lg,ly : OUT	STD_LOGIC_VECTOR(4 downto 1));
END COMPONENT;
COMPONENT sx
	PORT(
		sj : IN STD_LOGIC_VECTOR(3 downto 0);
		kz : IN STD_LOGIC;
		d : OUT	STD_LOGIC_VECTOR(6 downto 0));
END COMPONENT;
SIGNAL nsj : STD_LOGIC_VECTOR(4 downto 0);
SIGNAL nwk : STD_LOGIC_VECTOR(2 downto 0);
BEGIN
l_a: tbjsa PORT MAP (cpd,nsj);
l_b: tbjsb PORT MAP (cps,nwk);
l_c: dk PORT MAP (cpd,nsj(4 downto 1),lr,lg,ly);
l_d: sx PORT MAP (nsj(3 downto 0),nwk(0),d);
sel <= nwk;
END a;