seg7_lut_8_0.vhd

DE2开发平台7段显示VHDL代码

-- SEG7_LUT_8_0.vhd

-- This file was auto-generated as part of a SOPC Builder generate operation.
-- If you edit it your changes will probably be lost.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity SEG7_LUT_8_0 is
	port (
		CLK  : in  std_logic                     := '0';
		HEX0 : out std_logic_vector(6 downto 0);
		HEX1 : out std_logic_vector(6 downto 0);
		HEX2 : out std_logic_vector(6 downto 0);
		HEX3 : out std_logic_vector(6 downto 0);
		HEX4 : out std_logic_vector(6 downto 0);
		HEX5 : out std_logic_vector(6 downto 0);
		HEX6 : out std_logic_vector(6 downto 0);
		HEX7 : out std_logic_vector(6 downto 0);
		INPU : in  std_logic_vector(31 downto 0) := (others => '0');
		RS   : in  std_logic                     := '0';
		WR   : in  std_logic                     := '0'
	);
end entity SEG7_LUT_8_0;

architecture rtl of SEG7_LUT_8_0 is
	component SEG7_LUT_8 is
		port (
			CLK  : in  std_logic                     := 'X';
			HEX0 : out std_logic_vector(6 downto 0);
			HEX1 : out std_logic_vector(6 downto 0);
			HEX2 : out std_logic_vector(6 downto 0);
			HEX3 : out std_logic_vector(6 downto 0);
			HEX4 : out std_logic_vector(6 downto 0);
			HEX5 : out std_logic_vector(6 downto 0);
			HEX6 : out std_logic_vector(6 downto 0);
			HEX7 : out std_logic_vector(6 downto 0);
			INPU : in  std_logic_vector(31 downto 0) := (others => 'X');
			RS   : in  std_logic                     := 'X';
			WR   : in  std_logic                     := 'X'
		);
	end component SEG7_LUT_8;

begin

	seg7_lut_8_0 : component SEG7_LUT_8
		port map (
			WR   => WR,   -- avalon_slave_0.write
			INPU => INPU, --               .writedata
			CLK  => CLK,  --     clock_sink.clk
			RS   => RS,   --               .reset_n
			HEX0 => HEX0, --    conduit_end.export
			HEX1 => HEX1, --               .export
			HEX2 => HEX2, --               .export
			HEX3 => HEX3, --               .export
			HEX4 => HEX4, --               .export
			HEX5 => HEX5, --               .export
			HEX6 => HEX6, --               .export
			HEX7 => HEX7  --               .export
		);

end architecture rtl; -- of SEG7_LUT_8_0