tbjsb.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 32 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tbjsb IS
	PORT(
		cp : IN	STD_LOGIC;
		q : OUT	STD_LOGIC_VECTOR(2 downto 0));
END tbjsb;
ARCHITECTURE a OF tbjsb IS
COMPONENT JKFF
   PORT (j   : IN STD_LOGIC;
      k   : IN STD_LOGIC;
      clk : IN STD_LOGIC;
      clrn: IN STD_LOGIC;
      prn : IN STD_LOGIC;
      q   : OUT STD_LOGIC);
END COMPONENT;
SIGNAL vcc : STD_LOGIC;
SIGNAL njk,nq : STD_LOGIC_VECTOR(1 downto 0);
BEGIN
vcc <= '1';
njk(0) <= '1';
njk(1) <= nq(0);
l1:
FOR i IN 1 downto 0 GENERATE
n_jk: JKFF PORT MAP (njk(i),njk(i),cp,vcc,vcc,nq(i));
END GENERATE;
q(0) <= nq(0);
q(1) <= '0';
q(2) <= nq(1);
END a;