audiotop.vhd

audio file on virtex

-------------------------------------------------------------------------------
-- audiotop
--
-- Author(s):     James Brennan and Jorgen Peddersen
-- Created:       Dec 2000
-- Last Modified: Dec 2000
-- 
-- Map audio device to the RAM controller.  See other files for descriptions.
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity audiotop is
	port (
		clk: in STD_LOGIC;
		rstn: in STD_LOGIC;
		direction: in STD_LOGIC;
		speed: in STD_LOGIC_VECTOR(1 downto 0);	
		precision: in STD_LOGIC;
		volume: in STD_LOGIC_VECTOR(1 downto 0);
			
		CELeftn: out STD_LOGIC;
        CERightn: out STD_LOGIC;
        OELeftn: out STD_LOGIC;
        OERightn: out STD_LOGIC;
        WELeftn: out STD_LOGIC;
        WERightn: out STD_LOGIC;
        SRAMLeftAddr: out STD_LOGIC_VECTOR (18 downto 0);
        SRAMRightAddr: out STD_LOGIC_VECTOR (18 downto 0);
        SRAMLeftData: inout STD_LOGIC_VECTOR (15 downto 0);
        SRAMRightData: inout STD_LOGIC_VECTOR (15 downto 0);

		sdout: in STD_LOGIC;
		
		mclk: out STD_LOGIC;
        lrck: buffer STD_LOGIC;
        sclk: buffer STD_LOGIC;
        sdin: out STD_LOGIC;		

		recordStart: in STD_LOGIC;
		playStart: in STD_LOGIC;
		playStop : in STD_LOGIC;		
		full: out STD_LOGIC;
        done: out STD_LOGIC
);
end audiotop;

architecture audiotop_structure of audiotop is

component audio
    port (
        clk: in STD_LOGIC;
        rstn: in STD_LOGIC;
        sdout: in STD_LOGIC;
        recordStart: in STD_LOGIC;
        recordStop: in STD_LOGIC;
        playStart: in STD_LOGIC;
        playStop: in STD_LOGIC;
		direction: in STD_LOGIC;
		speed: in STD_LOGIC_VECTOR(1 downto 0);
		precision: in STD_LOGIC;
		volume: in STD_LOGIC_VECTOR(1 downto 0);
        dataIn: in STD_LOGIC_VECTOR(31 downto 0);
        mclk: out STD_LOGIC;
        lrck: buffer STD_LOGIC;
        sclk: buffer STD_LOGIC;
        sdin: out STD_LOGIC;
        recordAddress: out STD_LOGIC_VECTOR(18 downto 0);
        playAddress: out STD_LOGIC_VECTOR(18 downto 0);
        dataOut: out STD_LOGIC_VECTOR(31 downto 0);
        read: out STD_LOGIC;
        write: out STD_LOGIC;
        full: out STD_LOGIC;
        done: out STD_LOGIC
    );
end component;        

component sraminterface
    port (
        CLK: in STD_LOGIC;
        Resetn: in STD_LOGIC;
        doRead: in STD_LOGIC;
        doWrite: in STD_LOGIC;
        readAddr: in STD_LOGIC_VECTOR (18 downto 0);
        writeAddr: in STD_LOGIC_VECTOR (18 downto 0);
        readData: out STD_LOGIC_VECTOR (31 downto 0);
        writeData: in STD_LOGIC_VECTOR (31 downto 0);
        canRead: out STD_LOGIC;
        canWrite: out STD_LOGIC;
        CELeftn: out STD_LOGIC;
        CERightn: out STD_LOGIC;
        OELeftn: out STD_LOGIC;
        OERightn: out STD_LOGIC;
        WELeftn: out STD_LOGIC;
        WERightn: out STD_LOGIC;
        SRAMLeftAddr: out STD_LOGIC_VECTOR (18 downto 0);
        SRAMRightAddr: out STD_LOGIC_VECTOR (18 downto 0);
        SRAMLeftData: inout STD_LOGIC_VECTOR (15 downto 0);
        SRAMRightData: inout STD_LOGIC_VECTOR (15 downto 0)
    );
end component;

signal GND : STD_LOGIC;

-- invert the active low switches
signal invRecordStart : STD_LOGIC;
signal invPlayStart : STD_LOGIC;
signal invPlayStop : STD_LOGIC;

-- signals between RAM and audio
signal read : STD_LOGIC;
signal write : STD_LOGIC;
signal playAddress : STD_LOGIC_VECTOR(18 downto 0);
signal recordAddress : STD_LOGIC_VECTOR(18 downto 0);
signal playData : STD_LOGIC_VECTOR(31 downto 0);
signal recordData : STD_LOGIC_VECTOR(31 downto 0);

begin
	GND <= '0';
	
	-- switches are active low so invert them
	invRecordStart <= not recordStart;
	invPlayStart <= not playStart;
	invPlayStop <= not PlayStop;
	
	audioDevice : audio port map(
        clk => clk,
        rstn => rstn,
        sdout => sdout,
        recordStart => invRecordStart,
        recordStop => GND,
        playStart => invPlayStart,
        playStop => invPlayStop,
		direction => direction,
		speed => speed,
		precision => precision,
		volume => volume,
		dataIn => playData,
        mclk => mclk,
        lrck => lrck,
        sclk => sclk,
        sdin => sdin,
        recordAddress => recordAddress,
        playAddress => playAddress,
        dataOut => recordData,
        read => read,
        write => write,
        full => full,
        done => done
    );


	RAM : sraminterface port map(
        CLK => clk,
        Resetn => rstn,
        doRead => read,
        doWrite => write,
        readAddr => playAddress,
        writeAddr => recordAddress,
        readData => playData,
        writeData => recordData,
        canRead => open,
        canWrite => open,
        CELeftn => CELeftn,
        CERightn => CERightn,
        OELeftn => OELeftn,
        OERightn => OERightn,
        WELeftn => WELeftn,
        WERightn => WERightn,
        SRAMLeftAddr => SRAMLeftAddr,
        SRAMRightAddr => SRAMRightAddr,
        SRAMLeftData => SRAMLeftData,
        SRAMRightData => SRAMRightData
    );

end audiotop_structure;