encode.vhd

几个VHDL实现的源程序及其代码

library ieee;
use ieee.std_logic_1164.all;

entity encode is
port(
d: in std_logic_vector(7 downto 0);
ein : in std_logic;
a0n,a1n,a2n,gsn,eon : out std_logic);
end encode;

architecture behav of encode is
signal q : std_logic_vector(2 downto 0);
begin
a0n<=q(0);a1n<=q(1);a2n<=q(2);
process(d)
begin
if ein='1' then
q<="111";gsn<='1';eon<='1';
elsif d(7)='0' then
q<="000";gsn<='0';eon<='1';
elsif d(6)='0' then
q<="001";gsn<='0';eon<='1';
elsif d(5)='0' then
q<="010";gsn<='0';eon<='1';
elsif d(4)='0' then
q<="011";gsn<='0';eon<='1';
elsif d(3)='0' then
q<="100";gsn<='0';eon<='1';
elsif d(2)='0' then
q<="101";gsn<='0';eon<='1';
elsif d(1)='0' then
q<="110";gsn<='0';eon<='1';
elsif d(0)='0' then
q<="111";gsn<='0';eon<='1';
elsif d="11111111" then
q<="111";gsn<='1';eon<='0';
end if;
end process;
end behav;