remap.vhd

audio file on virtex

-------------------------------------------------------------------------------
-- remap.vhd
--
-- Created:       Dec 2000
-- Last Modified: Dec 2000
-- 
-- This file only renames signals to names that were in our ucf file at the
-- time.  It is not really required in the design.
-------------------------------------------------------------------------------


library IEEE;
use IEEE.std_logic_1164.all;

entity remap is
	port (
		CLK: in STD_LOGIC;
		PB: in STD_LOGIC_VECTOR(1 to 4);
		DIP: in STD_LOGIC_VECTOR(1 to 6);		
		Lsram_CEn: out STD_LOGIC;
        Rsram_CEn: out STD_LOGIC;
        Lsram_OEn: out STD_LOGIC;
        Rsram_OEn: out STD_LOGIC;
        Lsram_WEn: out STD_LOGIC;
        Rsram_WEn: out STD_LOGIC;
        Lsram_Addr: out STD_LOGIC_VECTOR (18 downto 0);
        Rsram_Addr: out STD_LOGIC_VECTOR (18 downto 0);
        Lsram_Data: inout STD_LOGIC_VECTOR (15 downto 0);
        Rsram_Data: inout STD_LOGIC_VECTOR (15 downto 0);

		Stereo_SDOUT: in STD_LOGIC;
		
		Stereo_MCLK: out STD_LOGIC;
        Stereo_LRCK: buffer STD_LOGIC;
        Stereo_SCLK: buffer STD_LOGIC;
        Stereo_SDIN: out STD_LOGIC;		

		BAR: out STD_LOGIC_VECTOR(8 to 9)
);
end remap;


architecture rename of remap is

component audiotop
	port (
		clk: in STD_LOGIC;
		rstn: in STD_LOGIC;
		direction: in STD_LOGIC;
		speed: in STD_LOGIC_VECTOR(1 downto 0);	
		precision: in STD_LOGIC;
		volume: in STD_LOGIC_VECTOR(1 downto 0);	
		CELeftn: out STD_LOGIC;
        CERightn: out STD_LOGIC;
        OELeftn: out STD_LOGIC;
        OERightn: out STD_LOGIC;
        WELeftn: out STD_LOGIC;
        WERightn: out STD_LOGIC;
        SRAMLeftAddr: out STD_LOGIC_VECTOR (18 downto 0);
        SRAMRightAddr: out STD_LOGIC_VECTOR (18 downto 0);
        SRAMLeftData: inout STD_LOGIC_VECTOR (15 downto 0);
        SRAMRightData: inout STD_LOGIC_VECTOR (15 downto 0);

		sdout: in STD_LOGIC;
		
		mclk: out STD_LOGIC;
        lrck: buffer STD_LOGIC;
        sclk: buffer STD_LOGIC;
        sdin: out STD_LOGIC;		

		recordStart: in STD_LOGIC;
        playStart: in STD_LOGIC;
        playStop: in STD_LOGIC;
		full: out STD_LOGIC;
        done: out STD_LOGIC
);
end component;

begin
	original : audiotop port map(
		clk => CLK,
		rstn => PB(1),
		direction => DIP(1),
		speed => DIP(2 to 3),
		precision => DIP(4),
		volume => DIP(5 to 6),
		
		CELeftn => Lsram_CEn,
        CERightn => Rsram_CEn,
        OELeftn => Lsram_OEn,
        OERightn => Rsram_OEn,
        WELeftn => Lsram_WEn,
        WERightn => Rsram_WEn,
        SRAMLeftAddr => Lsram_Addr,
        SRAMRightAddr => Rsram_Addr,
        SRAMLeftData => Lsram_Data,
        SRAMRightData => Rsram_Data,

		sdout => Stereo_SDOUT,
		
		mclk => Stereo_MCLK,
        lrck => Stereo_LRCK,
        sclk => Stereo_SCLK,
        sdin => Stereo_SDIN,

		recordStart => PB(4),
        playStart => PB(3),
        playStop => PB(2),
		full => BAR(8),
        done => BAR(9)
);
end rename;