代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/475342/6796704

vhd add-sub-and-or.vhd

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity ALU32 is port ( Opcode : in std_logic_vector(1 downto 0); SrcA : in std_logic
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www.eeworm.com/read/474293/6819241

vhd lock.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity lock is port(a:in std_logic_vector(9 downto 0); b:in std_logic_vector(9 downto 0); en,clk:in std_logic;
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vhd cpu8bit.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity CPU8bit is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC); end C
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txt 新建 文本文档.txt

entity top is Port (sysclk : in std_logic; reset : in std_logic; light_on : in std_logic; light_off : in std_logic; lcd_w : in std_logic; --when the button ispressed, t
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txt 新建 文本文档.txt

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vgacore is Port ( clk : in std_logic; reset : in std_logic;
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vhd top.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity top is generic(n:integer:=16); port(clk:in std_logic; clr:in std_logic; ena:in std_logic; di:in std_logic_vector(7
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vhdl jtop.vhdl

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity jtop is generic(n:integer:=16); port(clk:in std_logic; clr:in std_logic; ena:in std_logic; di:in std_logic_vector(
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vhd txmit_tb.vhd

-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000 -- -- Notes: -- 1) This testbench template has been automatically generated using types -- std_logic and std_logic_v
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txt 10.txt

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -----实体count10的说明 ENTITY COUNT10 IS PORT(CLK:IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); SEL:OUT STD_
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www.eeworm.com/read/472423/6867898

vhd ad.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AD IS PORT( DD:IN STD_LOGIC_VECTOR(7 DOWNTO 0); ST,EOC:IN STD_LOGIC; ALE,STA:OUT STD_LOGIC; OE,ADDA:OUT STD_LOGIC; QQ:OUT STD_LOGIC_VECTOR(7
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