add-sub-and-or.vhd

add sub. and or 加法 減法...........

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity ALU32 is
	port ( Opcode : in std_logic_vector(1 downto 0);
			SrcA : in std_logic_vector(31 downto 0);
			SrcB : in std_logic_vector(31 downto 0);
			ZF : out std_logic;
			CF : out std_logic;
			OvF : out std_logic;
			result : out std_logic_vector(31 downto 0));
end ALU32;
architecture ALU32_BEHAVIOUR of ALU32 is 
	signal B : std_logic_vector(31 downto 0); 
	signal S : std_logic_vector(31 downto 0);
	
begin
		process(SrcA, SrcB, Opcode)
		begin
			case Opcode is
				when "00" =>
					B <= SrcB;  
					S <= SrcA + SrcB;		
				when "01" =>
					B <= (not SrcB) + 1; 
					S <= SrcA + (not SrcB) + 1;
				when "10" =>  
					S <= SrcA and SrcB;			
				when "11" =>
					S <= SrcA or SrcB;		
			end case; 
			if S = "00000000000000000000000000000000" then
				ZF <= '1';
			else
				ZF <= '0';
			end if;
			if ((SrcA(31) = '1' or B(31) = '1') and S(31) = '0') or (SrcA(31) = '1' and B(31) = '1')then 
				CF <= '1';
			else
				CF <= '0';
			end if;
			if (SrcA(31) = '1' and B(31) = '1' and S(31) = '0') or (SrcA(31) = '0' and B(31) = '0' and S(31) = '1') then	
				OvF <= '1';          
			else
				OvF <= '0';
			end if;  
		end process;  
		result <= S; 

	
end ALU32_BEHAVIOUR;