cpu8bit.vhd

cpu8bit sourse code in vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity CPU8bit is
    Port ( clock : in  STD_LOGIC;
           reset : in  STD_LOGIC);
end CPU8bit;

architecture Behavioral of CPU8bit is
component ALU is
    Port ( accum : in  STD_LOGIC_VECTOR (7 downto 0);
           data : in  STD_LOGIC_VECTOR (7 downto 0);
           opcode : in  STD_LOGIC_VECTOR (3 downto 0);
           reset : in  STD_LOGIC;
           clock : in  STD_LOGIC;
           zero,carry : out  STD_LOGIC;
           alu_out : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component Accumulator is
    Port ( data : in  STD_LOGIC_VECTOR (7 downto 0);
           load : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           accum : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component MUX is
    Port ( IR_addr : in  STD_LOGIC_VECTOR (3 downto 0);
           PC_addr : in  STD_LOGIC_VECTOR (3 downto 0);
           addr_sel : in  STD_LOGIC;
			  address : out  STD_LOGIC_VECTOR (3 downto 0));
end component;

component ProgramCounter is
    Port ( Load : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
			  data : in  STD_LOGIC_VECTOR (3 downto 0);
           count : out  STD_LOGIC_VECTOR (3 downto 0));
end component;
component RAM is
	port(DataIn : in std_logic_vector(7 downto 0);
			DataOut : out std_logic_vector(7 downto 0);
			Address : in std_logic_vector(3 downto 0);
			RW, CS, CLK : in std_logic);
end component;
component control_unit is
    Port ( Clk : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           Zero : in  STD_LOGIC;
			  carry : in  STD_LOGIC;
           Opcode : in  STD_LOGIC_VECTOR (3 downto 0);
           Addr_sel : out  STD_LOGIC;
           rd : out  STD_LOGIC;
           wr : out  STD_LOGIC;
           load_ir : out  STD_LOGIC;
           load_acc : out  STD_LOGIC;
           load_pc : out  STD_LOGIC;
           inc_pc : out  STD_LOGIC;
           halt : out  STD_LOGIC;
           aluout_en : out  STD_LOGIC);
end component;

component reg is
    Port ( data : in  STD_LOGIC_VECTOR (7 downto 0);
           ena : in  STD_LOGIC;
           rstn : in  STD_LOGIC;
           clkp : in  STD_LOGIC;
           reg_out : out  STD_LOGIC_VECTOR (7 downto 0));	
end component;	

signal alu_out_1,accum_1,data_1,data_out_1,reg_out_1 :STD_LOGIC_VECTOR (7 downto 0);
signal opcode_1,addressIR_1,PC_addr_1,Address_1 :STD_LOGIC_VECTOR (3 downto 0); 
signal zero_1,carry_1,load_acc1,Addr_sel_1,rd_1,wr_1,load_ir_1,load_pc_1,inc_pc_1,halt_1,aluout_en_1 :STD_LOGIC; 
begin

opcode_1<=reg_out_1(7 downto 4);
addressIR_1<=reg_out_1(3 downto 0);

ALU1:ALU  port map(accum_1,data_out_1,opcode_1,reset,clock,zero_1,carry_1,alu_out_1);
Accumulator1:Accumulator  port map(alu_out_1,load_acc1,clock,reset,accum_1);
control_unit1:control_unit  port map(clock,reset,zero_1,carry_1,opcode_1,Addr_sel_1,rd_1,wr_1,load_ir_1
												,load_acc1,load_pc_1,inc_pc_1,halt_1,aluout_en_1);
ProgramCounter1:ProgramCounter port map(load_pc_1,reset,clock,addressIR_1,PC_addr_1);
RAM1:RAM port map(alu_out_1,data_out_1,Address_1,wr_1,'1',clock);
Instruction:reg port map(data_out_1,load_ir_1,reset,clock,reg_out_1);
MUX1:MUX port map(addressIR_1,PC_addr_1,Addr_sel_1,Address_1);

end Behavioral;