📄 新建 文本文档.txt
字号:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgacore is
Port ( clk : in std_logic;
reset : in std_logic;
md : in std_logic_vector(1 downto 0);
hs : out std_logic;
vs : out std_logic;
r : out std_logic_vector(1 downto 0);
g : out std_logic_vector(2 downto 0);
b : out std_logic_vector(2 downto 0)
);
end vgacore;
architecture Behavioral of vgacore is
signal sysclk : std_logic;
signal hsyncb : std_logic;
signal vsyncb : std_logic;
signal enable : std_logic;
signal hloc : std_logic_vector(9 downto 0);
signal vloc : std_logic_vector(9 downto 0);
signal rgbx,rgby,rgbp,rgb: std_logic_vector(7 downto 0);
--定义VGASIG元件，产生同步信号进行行、场扫描，即显示驱动
component vgasig
Port (
clock : in std_logic;
reset : in std_logic;
hsyncb : buffer std_logic;
vsyncb : out std_logic;
enable : out std_logic;
Xaddr : out std_logic_vector(9 downto 0);
Yaddr : out std_logic_vector(9 downto 0)
);
end component;
--定义colormap元件，确定颜色及位置信息
component colormap
Port (
hloc : in std_logic_vector(9 downto 0);
vloc : in std_logic_vector(9 downto 0);
rgbx : out std_logic_vector(7 downto 0);
rgby : out std_logic_vector(7 downto 0)
);
end component;
begin
rgb(7) <= rgbp(7) and enable;
rgb(6) <= rgbp(6) and enable;
rgb(5) <= rgbp(5) and enable;
rgb(4) <= rgbp(4) and enable;
rgb(3) <= rgbp(3) and enable;
rgb(2) <= rgbp(2) and enable;
rgb(1) <= rgbp(1) and enable;
rgb(0) <= rgbp(0) and enable;
--产生25Mhz的像素输出频率
divclk: process(clk,reset)
begin
if reset='0' then
sysclk <= '0';
elsif clk'event and clk='1' then
sysclk <= not sysclk;
end if;
end process;
--模式选择单元：本测试程序我们使用了4种模式，由KEY_B2,KEY_B3控制，当选择模式"11"时，即不按下B2，B3，VGA显示竖彩条；当选择模式"00"时，即同时按下B2，B3时，VGA显示全黑；当选择模式"01"时，即只按下B2时，VGA显示横彩条；当选择模式"10"时，即只按下B3时，VGA时显示横竖彩条。
modchoice: process(md,rgbx,rgby)
begin
if md="11" then rgbp <= rgbx;
elsif md="01" then rgbp <= rgby;
elsif md="10" then rgbp <= rgbx xor rgby;
else rgbp <= "00000000";
end if;
end process;
makesig: vgasig Port map(
clock => sysclk,
reset => reset,
hsyncb => hsyncb,
vsyncb => vsyncb,
enable => enable,
Xaddr => hloc,
Yaddr => vloc
);
makergb: colormap Port map(
hloc => hloc,
vloc => vloc,
rgbx => rgbx,
rgby => rgby
);
hs <= hsyncb;
vs <= vsyncb;
r <= rgb(7 downto 6);
g <= rgb(5 downto 3);
b <= rgb(2 downto 0);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgasig is
Port ( clock : in std_logic;
reset : in std_logic;
hsyncb: buffer std_logic;
vsyncb: out std_logic;
enable: out std_logic;
Xaddr : out std_logic_vector(9 downto 0);
Yaddr : out std_logic_vector(9 downto 0));
end vgasig;
architecture Behavioral of vgasig is
--定义相关常量，可参考VGA相关工业标准
constant H_PIXELS: INTEGER:=640;
constant H_FRONT: INTEGER:=16;
constant H_BACK: INTEGER:=48;
constant H_SYNCTIME:INTEGER:=96;
constant H_PERIOD: INTEGER:= H_SYNCTIME + H_PIXELS + H_FRONT + H_BACK;
constant V_LINES: INTEGER:=480;
constant V_FRONT: INTEGER:=11;
constant V_BACK: INTEGER:=32;
constant V_SYNCTIME: INTEGER:=2;
constant V_PERIOD: INTEGER:= V_SYNCTIME + V_LINES + V_FRONT + V_BACK;
signal hcnt: std_logic_vector(9 downto 0); -- 行计数器
signal vcnt: std_logic_vector(9 downto 0); -- 场计数器
begin
--产生行计数（记录每行的点数），H_PERIOD 为行周期计数值。
A: process(clock, reset)
begin
--复位时行计数器清零
if reset = '0' then
hcnt <= (others => '0');
elsif (clock'event and clock = '1') then
--当行计数到达计数周期时将重置
if hcnt < H_PERIOD then
hcnt <= hcnt + 1;
else
hcnt <= (others => '0');
end if;
end if;
end process;
--产生场记数（记录每帧中的行数），V_PERIOD为场周期计数值
B: process(hsyncb, reset)
begin
-- 复位场计数器清零
if reset='0' then
vcnt <= (others => '0');
elsif (hsyncb'event and hsyncb = '1') then
if vcnt < V_PERIOD then
vcnt <= vcnt + 1;
else
vcnt <= (others => '0');
end if;
end if;
end process;
--产生行同步信号，H_PIXELS为行显示点数，H_FRONT为前消隐点数，H_SYNCTIME为行同步点数
C: process(clock, reset)
begin
if reset = '0' then
hsyncb <= '1';
elsif (clock'event and clock = '1') then
if (hcnt >= (H_PIXELS + H_FRONT) and hcnt < (H_PIXELS + H_SYNCTIME + H_FRONT)) then
hsyncb <= '0';
else
hsyncb <= '1';
end if;
end if;
end process;
--产生场同步信号，V_LINES为场显示点数，V_FRONT为前消隐点数，V_SYNCTIME场同步点数
D: process(hsyncb, reset)
begin
if reset = '0' then
vsyncb <= '1';
elsif (hsyncb'event and hsyncb = '1') then
if (vcnt >= (V_LINES + V_FRONT) and vcnt < (V_LINES + V_SYNCTIME + V_FRONT)) then
vsyncb <= '0';
else
vsyncb <= '1';
end if;
end if;
end process;
E: process (clock)
begin
if clock'EVENT and clock = '1' then
-- 此处enable为低
if hcnt >= H_PIXELS or vcnt >= V_LINES then
enable <= '0';
else
enable <= '1';
end if;
end if;
end process;
H:
Xaddr <= hcnt;
Yaddr <= vcnt;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity colormap is
Port ( hloc : in std_logic_vector(9 downto 0);
vloc : in std_logic_vector(9 downto 0);
rgbx : out std_logic_vector(7 downto 0);
rgby : out std_logic_vector(7 downto 0));
end colormap;
architecture Behavioral of colormap is
begin
--然后产生彩条信号，下面是竖彩条的产生，横彩条、方格等信号产生类似。
process(hloc,vloc)
begin
case hloc(7 downto 5) is
when "000" => rgbx <= "11111111";
when "001" => rgbx <= "00000000";
when "010" => rgbx <= "11000000";
when "011" => rgbx <= "00000111";
when "100" => rgbx <= "00111000";
when "101" => rgbx <= "11000111";
when "110" => rgbx <= "11111000";
when "111" => rgbx <= "11111111";
when others => rgbx <= "00000000";
end case;
case vloc(7 downto 5) is
when "000" => rgby <= "10101010";
when "001" => rgby <= "01010101";
when "010" => rgby <= "11001110";
when "011" => rgby <= "00110001";
when "100" => rgby <= "00101110";
when "101" => rgby <= "01100110";
when "110" => rgby <= "11111100";
when "111" => rgby <= "00011110";
when others => rgby <= "00000000";
end case;
end process;
end Behavioral;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -