top.vhd

这是一个交织器/解交织器的FPGA实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity top is
generic(n:integer:=16);
port(clk:in std_logic;
		clr:in std_logic;
		ena:in std_logic;
		di:in std_logic_vector(7 downto 0);
		do:out std_logic_vector(7 downto 0));
end top;

architecture rtl of top is
    
component countern
port(clr,ena,clk:in std_logic;
	  q:buffer integer range 0 to n-1;		
	  cout:out std_logic);
end component;


component rom_16_8
port(addr:in integer range 0 to n-1;
	  clk:in std_logic;
	  data:out std_logic_vector(7 downto 0));
end component;


component mux2
port(d0:in std_logic_vector(7 downto 0);
	  d1:in integer range 0 to n-1;
	  sel:in std_logic;
	  yout:out std_logic_vector(7 downto 0));
end component;    



component ram_16_8
port(ad:in std_logic_vector(7 downto 0);			
	  clk:in std_logic;
	  di:in std_logic_vector(7 downto 0);				
	  do:out std_logic_vector(7  downto 0);				
	  wr_en:in std_logic:='0';													
	  rd_en:in std_logic:='0');											
end component;

signal qs:integer range 0 to n-1:=0;
signal ds:std_logic_vector(7 downto 0);
signal ys:std_logic_vector(7 downto 0);
signal cout:std_logic;
signal wr_en:std_logic:='0';
signal rd_en:std_logic:='0';
signal sel:std_logic:='0';

begin
	ct:countern
	port map(clk=>clk,
				clr=>clr,
				ena=>ena,
				cout=>cout,
				q=>qs);
				
	rom:rom_16_8
	port map(clk=>clk,
				addr=>qs,
				data=>ds);
	mux:mux2
	port map(d1=>qs,
				d0=>ds,
				sel=>sel,
				yout=>ys);
				
	rma:ram_16_8
	port map(clk=>clk,
				do=>do,
				di=>di,
				wr_en=>wr_en,
				rd_en=>rd_en,
				ad=>ys);
				
	process(cout)
		begin
			if cout'event and cout='0' then
				sel<=not sel;
			end if;
			if sel='1' then
				wr_en<='1';
			else rd_en<='1';
			end if;
	end process;
end rtl;