ad.vhd

来自「几个VHDL实现的源程序及其代码」· VHDL 代码 · 共 62 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY AD IS
PORT(
DD:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ST,EOC:IN STD_LOGIC;
ALE,STA:OUT STD_LOGIC;
OE,ADDA:OUT STD_LOGIC;
QQ:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END AD;

ARCHITECTURE BEHAV OF AD IS
SIGNAL QQQ: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DK,CLR: STD_LOGIC;
BEGIN
ADDA<='1';
OE<=NOT EOC;
CLR<=NOT EOC;
PROCESS(EOC)
BEGIN
IF EOC'EVENT AND EOC='1' THEN
QQQ<=DD;
END IF;
END PROCESS;
PROCESS(CLR,ST)
BEGIN
IF CLR='1' THEN
DK<='0';
ELSIF ST'EVENT AND ST='1' THEN
DK<='1';
END IF;
END PROCESS;
ALE<=DK;
STA<=DK;
QQ<=QQQ;
END BEHAV;