代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/154365/11966887

vhd jfq.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; USE IEEE.STD_LOGIC_ARITH.ALL; entity JFQ is port ( CLKSIN,CLK,CONLINK,RESET,clk100:in std_logic; time
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www.eeworm.com/read/154365/11966899

vhd xiaodou.vhd

Library ieee; use ieee.std_logic_1164.all; entity xiaodou is port ( clk,a:in std_logic; aa :OUT STD_LOGIC ); end; architecture behv of xiaodou is SIGNAL C
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www.eeworm.com/read/154362/11966995

vhd maxout.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MAXOUT IS PORT ( JIASHUIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
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www.eeworm.com/read/154362/11967001

vhd maxstartxt.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MAXSTARTXT IS PORT( XIN,YIN : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
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www.eeworm.com/read/154362/11967016

vhd control.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY CONTROL IS PORT( CLK,RESET,SET : IN STD_LOGIC; ADIN : IN STD_LOGIC_
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www.eeworm.com/read/256600/11983671

vhd uart_clock.vhd

-- -- KCPSM3 reference design - Real Time Clock with UART communications -- -- Ken Chapman - Xilinx Ltd - October 2003 -- -- The design demonstrates the following:- -- Connection of KC
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www.eeworm.com/read/256595/11983925

vhd pico_test.vhd

----------------------------------------------------------------- -- -- Pico_test.vhd -- -- Author: Nial Stewart, Nial Stewart Developments Ltd. -- www.nialstewart.co.uk -- J
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www.eeworm.com/read/256595/11983930

vhd kcpsm.vhd

-- Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices -- -- Version : 1.00c -- Version Date : 14th August 2002 -- -- Start of design entry : 2nd July 2002 -- -- K
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www.eeworm.com/read/342479/12016844

vhd m10.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity m10 is port( clk,reset:in std_logic; cout:out std_logic_vector(3 downto 0); c
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www.eeworm.com/read/342479/12018604

vhd lock.vhd

library ieee; use ieee.std_logic_1164.all; entity lock is port( in0,in1,in2,in3:in std_logic_vector(3 downto 0); clk : in std_logic; out0,out1,out2,out3:out std_logic_vector(3 downto 0)
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