📄 xiaodou.vhd
字号:
Library ieee;
use ieee.std_logic_1164.all;
entity xiaodou is
port (
clk,a:in std_logic;
aa :OUT STD_LOGIC
);
end;
architecture behv of xiaodou is
SIGNAL CO1,o1,o2,q: STD_LOGIC;
BEGIN
process(a,clk)
begin
o1<=not(a or o2);
o2<=not(q or o1);
if clk'event and clk='1'
then q<=o2;
end if;
aa<=q;
END PROCESS;
END ;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -