📄 jfq.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity JFQ is
port (
CLKSIN,CLK,CONLINK,RESET,clk100:in std_logic;
time_3,time_2,time_1,time_0:in integer range 9 downto 0;
dataout:out integer range 9 downto 0;
selout :out integer range 0 to 7 );
end;
architecture behv of JFQ is
signal COFL,CO1,CO2,KM1,JIANCE1,CON,CLKS:STD_LOGIC;
SIGNAL MONEY1,MONEY2,MONEY3,MONEY4: INTEGER RANGE 9 DOWNTO 0 ;
COMPONENT JFQ1
port (
CLKS,CLK,COF,CON,KM,RESET,JIANCE:in std_logic;
COUT1 :OUT STD_LOGIC;
MONEY1,MONEY2:OUT INTEGER RANGE 9 DOWNTO 0 );
END COMPONENT;
COMPONENT JFQ2
port (
CLK2,RESET,CON:in std_logic;
COUT2 :OUT STD_LOGIC;
MONEY3:OUT INTEGER RANGE 9 DOWNTO 0 );
END COMPONENT;
COMPONENT JFQ3
port ( CLK3,RESET,CON:in std_logic;
COF :OUT STD_LOGIC;
MONEY4:OUT INTEGER RANGE 9 DOWNTO 0 );
END COMPONENT;
COMPONENT KM
port (
CLK,RESET,CON:in std_logic;
COUT:OUT STD_LOGIC
);
END COMPONENT;
COMPONENT JIANCE
port (
CLKS,CLK:in std_logic;
-- OUTY :OUT INTEGER RANGE 9 DOWNTO 0;
--RESET,CNT_EN,LOAD1: OUT STD_LOGIC;
COUT: OUT STD_LOGIC
);
END COMPONENT;
COMPONENT FENPIN
PORT ( clk:in std_logic;
fout:out std_logic);
end COMPONENT;
COMPONENT START
port ( CON_EN:in std_logic;
CON:out std_logic);
END COMPONENT;
COMPONENT yima is
port ( time_3,time_2,time_1,time_0:in integer range 9 downto 0;
money_3,money_2,money_1,money_0:in integer range 9 downto 0;
clk:in std_logic;
data_out:out integer range 9 downto 0;
selout :out integer range 0 to 7);
end COMPONENT ;
--component xiaodou is
--port (
-- clk,a:in std_logic;
-- aa :OUT STD_LOGIC
-- );
--end component;
BEGIN
U0: FENPIN PORT MAP(CLK=>CLKSIN,FOUT=>CLKS);
U1: JFQ1 PORT MAP(CLK=>CLK,CLKS=>CLKS,COF=>COFL,CON=>CON,RESET=>RESET,MONEY1=>MONEY1,MONEY2=>MONEY2,COUT1=>CO1,KM=>KM1,JIANCE=>JIANCE1);
U2: JFQ2 PORT MAP(CLK2=>CO1,CON=>CON,RESET=>RESET,MONEY3=>MONEY3,COUT2=>CO2);
U3: JFQ3 PORT MAP(CLK3=>CO2,COF=>COFL,CON=>CON,RESET=>RESET,MONEY4=>MONEY4);
U4: KM PORT MAP(CLK=>CLKS,COUT=>KM1,CON=>CON,RESET=>RESET);
U5: JIANCE PORT MAP(CLK=>CLK,CLKS=>CLKS,COUT=>JIANCE1);
U6: START PORT MAP(CON_EN=>CONLINK,CON=>CON);
U7: YIMA PORT MAP(time_3=>time_3,time_2=>time_2,time_1=>time_1,time_0=>time_0,money_3=>MONEY4,money_2=>MONEY3,money_1=>MONEY2,money_0=>MONEY1,clk=>clk100,data_out=>dataout,selout=>selout);
--U8: XIAODOU PORT MAP(a=>CON_EN,clk=>clk100,aa=>CONLINK);
END ;
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