lock.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;

entity lock is 
port(
in0,in1,in2,in3:in std_logic_vector(3 downto 0);
clk : in std_logic;
out0,out1,out2,out3:out std_logic_vector(3 downto 0)
     );
end lock;

architecture behavior of lock is
begin
  process(clk)
    begin
      if (clk'event and clk='1')then
          out0<=in0;
          out1<=in1;
          out2<=in2;

          out3<=in3;
      end if;
  end process;
end behavior;