m10.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity m10 is
port(
clk,reset:in std_logic;
cout:out std_logic_vector(3 downto 0);
co:out std_logic
    );
end m10;

architecture behavior of m10 is
signal cot:std_logic;
signal temp:std_logic_vector(3 downto 0);
begin
   process(clk,reset)
     begin
       if reset='1' then
           cot<='0';
           temp<="0000";
         elsif (clk'event and clk='1')then
           if temp="1001" then
              temp<="0000";
              cot<='1';
             else temp<=temp+1;
                cot<='0';
           end if;
        end if;
   end process;
co<=cot;
cout<=temp;
end behavior;