maxout.vhd

使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MAXOUT IS 
   PORT 
       ( JIASHUIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
         Z1IN :IN STD_LOGIC_VECTOR(8 DOWNTO 0);
         SOUTIN :  IN STD_LOGIC;
         SHUCHU : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END ;
ARCHITECTURE HDLARCH OF MAXOUT IS

COMPONENT ADD8 IS 
   PORT 
       ( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 C : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) );
END COMPONENT;

SIGNAL STMP : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL LINSHI: STD_LOGIC;

BEGIN 

LINSHI<='0';

U1 : ADD8 PORT MAP(A(0 TO 7)=>Z1IN(0 TO 7),B(0 TO 6 )=>JIASHUIN(0 TO 6),B(7)=>LINSHI,C=>STMP);
      

SHUCHU(0) <= (((NOT SOUTIN) AND STMP(0)) OR (SOUTIN AND Z1IN(0))) OR Z1IN(8) OR STMP(8);
SHUCHU(1) <= (((NOT SOUTIN) AND STMP(1)) OR (SOUTIN AND Z1IN(1))) OR Z1IN(8) OR STMP(8);
SHUCHU(2) <= (((NOT SOUTIN) AND STMP(2)) OR (SOUTIN AND Z1IN(2))) OR Z1IN(8) OR STMP(8);
SHUCHU(3) <= (((NOT SOUTIN) AND STMP(3)) OR (SOUTIN AND Z1IN(3))) OR Z1IN(8) OR STMP(8);
SHUCHU(4) <= (((NOT SOUTIN) AND STMP(4)) OR (SOUTIN AND Z1IN(4))) OR Z1IN(8) OR STMP(8);
SHUCHU(5) <= (((NOT SOUTIN) AND STMP(5)) OR (SOUTIN AND Z1IN(5))) OR Z1IN(8) OR STMP(8);
SHUCHU(6) <= (((NOT SOUTIN) AND STMP(6)) OR (SOUTIN AND Z1IN(6))) OR Z1IN(8) OR STMP(8);
SHUCHU(7) <= (((NOT SOUTIN) AND STMP(7)) OR (SOUTIN AND Z1IN(7))) OR Z1IN(8) OR STMP(8);


END;