control.vhd

来自「使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真」· VHDL 代码 · 共 43 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CONTROL IS
   PORT( CLK,RESET,SET : IN STD_LOGIC;
         ADIN  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
         ADOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         WR  : OUT STD_LOGIC );
END;
ARCHITECTURE BEHV OF CONTROL IS



BEGIN

PROCESS( CLK,RESET,ADIN,SET)
VARIABLE STMP : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE WORR : STD_LOGIC;
BEGIN 
IF RESET ='1' THEN STMP:="00000000";
 ELSIF SET='1' THEN STMP:=ADIN; WORR:='0';

ELSIF  CLK'EVENT AND CLK  ='1'  THEN 
 
   WORR:=NOT WORR; 
  
IF WORR='1' THEN STMP:=STMP+1; END IF; 
END IF;



ADOUT<=STMP;

WR<=WORR;


END PROCESS;

END;