maxstartxt.vhd

来自「使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真」· VHDL 代码 · 共 49 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY MAXSTARTXT IS 
     PORT(   XIN,YIN : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
             KIN :IN STD_LOGIC_VECTOR(6 DOWNTO 0);
             SOUTPUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;
ARCHITECTURE BEHV OF MAXSTARTXT IS
COMPONENT max IS 
   PORT 
       ( X,Y : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
           Z1,Z2 : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) );
END COMPONENT;
COMPONENT MAXOUT IS 
   PORT 
       ( JIASHUIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
         Z1IN :IN STD_LOGIC_VECTOR(8 DOWNTO 0);
         SOUTIN :  IN STD_LOGIC;
         SHUCHU : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END COMPONENT;
COMPONENT ksubabs IS 
   PORT 
       ( ABSXY,K: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
                 SOUT : OUT STD_LOGIC;
         jiashu : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END COMPONENT;
COMPONENT ABSXY IS 
   PORT 
       ( X,Y : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
       QUXY : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END COMPONENT;


SIGNAL STMP1,STMP2 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL STMP3,STMP5 : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL STMP4 : STD_LOGIC;
BEGIN

U1 : MAX PORT MAP(X=>XIN,Y=>YIN,Z1=>STMP1,Z2=>STMP2);
u2 : ABSXY PORT MAP(X=>STMP1,Y=>STMP2,QUXY=>STMP3);
U3 : KSUBABS PORT MAP(ABSXY=>STMP3,K=>KIN,SOUT=>STMP4,JIASHU=>STMP5);
U4 : MAXOUT PORT MAP(JIASHUIN=>STMP5,Z1IN=>STMP1,SOUTIN=>STMP4,SHUCHU=>SOUTPUT);

END;